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Unformatted text preview: CSE 141 Dean Tullsen Control Logic for the Single-Cycle CPU or Who’s in charge here? CSE 141 Dean Tullsen Putting it All Together: A Single Cycle Datapath • We have everything except control signals MemtoReg MemRead MemWrite ALUOp ALUSrc RegDst PC Instruction& memory Read& address Instruction& [31–0] Instruction [20–16] Instruction [25–21] Add Instruction [5–0] RegWrite 4 16 32 Instruction [15–0] Registers Write& register Write& data Write& data Read& data 1 Read& data 2 Read& register 1 Read& register 2 Sign& extend ALU& result Zero Data& memory Address Read& data M& u& x 1 M& u& x 1 M& u& x 1 M& u& x 1 Instruction [15–11] ALU& control Shift& left 2 PCSrc ALU Add ALU& result CSE 141 Dean Tullsen Okay, then, what about those Control Signals? PC Instruction& memory Read& address Instruction& [31–0] Instruction [20 16] Instruction [25 21] Add Instruction [5 0] MemtoReg ALUOp MemWrite RegWrite MemRead Branch RegDst ALUSrc Instruction [31 26] 4 16 32 Instruction [15 0] M& u& x 1 Control Add ALU& result M& u& x 1 Registers Write& register Write& data Read& data 1 Read& data 2 Read& register 1 Read& register 2 Sign& extend M& u& x 1 ALU& result Zero PCSrc Data& memory Write& data Read& data M& u& x 1 Instruction [15 11] ALU& control Shift& left 2 ALU Address CSE 141 Dean Tullsen ALU control bits • Recall: 5-function ALU • based on (bits 31-26) and code (bits 5-0) from instruction...
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This note was uploaded on 02/14/2008 for the course CSE 141 taught by Professor Tullsen during the Fall '06 term at UCSD.
- Fall '06
- Computer Architecture