lect6 pipeline

Lect6 pipeline - CSE 141 Dean Tullsen Designing a Pipelined CPU CSE 141 Dean Tullsen Instruction Latencies and Throughput • Single-Cycle CPU •

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Unformatted text preview: CSE 141 Dean Tullsen Designing a Pipelined CPU CSE 141 Dean Tullsen Instruction Latencies and Throughput • Single-Cycle CPU • Multiple Cycle CPU • Pipelined CPU Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Ifetch Reg/Dec Exec Mem Wr Load Ifetch Reg/Dec Exec Mem Wr Load Ifetch Reg/Dec Exec Mem Wr Load Ifetch Reg/Dec Exec Mem Wr Load Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Ifetch Reg/Dec Exec Mem Wr Load Ifetch Reg/Dec Exec Mem Wr Load CSE 141 Dean Tullsen Pipelining Advantages • Higher throughput • Higher of CPU resources • But, more complicated datapath , more complex control(?) CSE 141 Dean Tullsen Pipelining Advantages CPU Design Technology Single-Cycle CPU Multiple-Cycle CPU Pipelined CPU Control Logic Combinational Logic FSM or Microprogram Peak Throughput 1 1 1 CSE 141 Dean Tullsen Pipelining in Modern CPUs • CPU Datapath • Arithmetic Units • System Buses • Software (at multiple levels) • etc... CSE 141 Dean Tullsen A Pipelined Datapath IF: Instruction fetch ID: Instruction decode and register fetch EX: Execution and effective address calculation MEM: Memory access WB: Write back Pipelined Datapath Instruction& memory Address 4 32 Add Add& result Shift& left 2 Instruction M& u& x 1 Add PC Write& data M& u& x 1 Registers Read& data 1 Read& data 2 Read& register 1 Read& register 2 16 Sign& extend Write& register Write& data Read& data Address Data& memory 1 ALU& result M& u& x ALU Zero IF: Instruction fetch ID: Instruction decode/& register file read EX: Execute/& address calculation MEM: Memory access WB: Write back CSE 141 Dean Tullsen Execution in a Pipelined Datapath IM Reg A L U DM Reg IM Reg A L U DM Reg IM Reg A L U DM Reg IM Reg A L U DM Reg IM Reg A L U DM Reg CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 lw lw lw lw lw steady state steady state IF ID EX MEM WB IF ID EX MEM WB CSE 141 Dean Tullsen Mixed Instructions in the Pipeline IM Reg A L U Reg IM Reg A L U DM Reg CC1 CC2 CC3 CC4 CC5 CC6 lw add CSE 141 Dean Tullsen Pipeline Principles • All instructions that share a pipeline must have the same _______ in the same __________ ....
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This note was uploaded on 02/14/2008 for the course CSE 141 taught by Professor Tullsen during the Fall '06 term at UCSD.

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Lect6 pipeline - CSE 141 Dean Tullsen Designing a Pipelined CPU CSE 141 Dean Tullsen Instruction Latencies and Throughput • Single-Cycle CPU •

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