lect6 -advance pipelining

lect6 -advance pipelining - Pipelining and Exceptions...

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CSE 141 Dean Tullsen Advanced Pipelining CSE 141 Dean Tullsen Pipelining and Exceptions Exceptions represent another form of control dependence. Therefore, they create a potential branch hazard Exceptions must be recognized early enough in the pipeline that subsequent instructions can be flushed before they change any permanent state. As long as we do that, everything else works the same as before. Exception-handling that always correctly identifies the offending instruction is called precise interrupts . CSE 141 Dean Tullsen Pipelining in Today’s Most Advanced Processors Not fundamentally different than the techniques we discussed Deeper pipelines Pipelining is combined with – superscalar execution – out-of-order execution – VLIW (very-long-instruction-word) CSE 141 Dean Tullsen Superscalar Execution IM Reg ALU DM Reg IM Reg DM Reg IM Reg DM Reg IM Reg DM Reg IM Reg DM Reg IM Reg DM Reg IM Reg DM Reg IM Reg DM Reg IM Reg DM Reg IM Reg DM Reg IM Reg DM Reg
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CSE 141 Dean Tullsen A modest superscalar MIPS what can this machine do in parallel? what other logic is required?
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This note was uploaded on 02/14/2008 for the course CSE 141 taught by Professor Tullsen during the Fall '06 term at UCSD.

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lect6 -advance pipelining - Pipelining and Exceptions...

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