lec2 instruction set architecture

lec2 instruction set architecture - Brief Vocabulary Lesson...

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CSE 141 Dean Tullsen Instruction Set Architecture or “How to talk to computers if you aren’t in Star Trek” CSE 141 Dean Tullsen Brief Vocabulary Lesson superscalar processor -- can execute more than one instruction per cycle. cycle -- smallest unit of time in a processor. parallelism -- the ability to do more than one thing at once. pipelining -- overlapping parts of a large task to increase throughput without decreasing latency CSE 141 Dean Tullsen Key ISA decisions • operations ± how many? ± which ones • operands ± how many? ± location ± types ± how to specify? • instruction format ± size ± how many formats? y = x + b operation source operands destination operand how does the computer know what 0001 0100 1101 1111 means? (add r1, r2, r5) CSE 141 Dean Tullsen Crafting an ISA We’ll look at some of the decisions facing an instruction set architect, and how those decisions were made in the design of the MIPS instruction set.
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CSE 141 Dean Tullsen Instruction Length Variable: Fixed: Hybrid: CSE 141 Dean Tullsen Instruction Length Variable-length instructions (Intel 80x86, VAX) require multi-step fetch and decode, but allow for a much more flexible and compact instruction set. Fixed-length instructions allow easy fetch and decode, and simplify pipelining and parallelism. F All MIPS instructions are 32 bits long. – this decision impacts every other ISA decision we make because it makes instruction bits scarce. CSE 141 Dean Tullsen Instruction Formats -what does each bit mean? • Having many different instruction formats. .. • complicates decoding • uses more instruction bits (to specify the format) VAX 11 instruction format CSE 141 Dean Tullsen MIPS Instruction Formats the tells the machine which format so add r1, r2, r3 has – opcode=0, funct=32, rs=2, rt=3, rd=1, sa=0 – 000000 00010 00011 00001 00000 100000 opcode opcode opcode rs rt rd sa funct rs rt immediate target 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
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CSE 141 Dean Tullsen Accessing the Operands operands are generally in one of two places: – registers (32 int, 32 fp) – memory (2 32 locations) registers are the idea that we want to access registers whenever possible led to load-store architectures . – normal arithmetic instructions only access registers – only access memory with explicit loads and stores CSE 141 Dean Tullsen Load-store architectures can do: add r1=r2+r3 and load r3, M(address) forces heavy dependence on registers, which is exactly what you want in today’s CPUs can’t do add r1 = r2 + M(address) - + CSE 141 Dean Tullsen How Many Operands?
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This note was uploaded on 02/14/2008 for the course CSE 141 taught by Professor Tullsen during the Fall '06 term at UCSD.

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lec2 instruction set architecture - Brief Vocabulary Lesson...

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