EE 435 HW 2 Sol Spring 2014

EE 435 HW 2 Sol Spring 2014 - Page 1 of 12 Page 2 of 12...

Info icon This preview shows pages 1–9. Sign up to view the full content.

Page 1 of 12
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

Page 2 of 12
Image of page 2
Page 3 of 12
Image of page 3

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

Page 4 of 12
Image of page 4
Page 5 of 12
Image of page 5

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

Page 6 of 12 Problem 8&9 For this problem, here just providing an example on how to generate . v sL curve. Taking a) as an example min 100 ; 1.5 ; 5 EB DS EB V mV W W mV V Using the calculator in cadence to get the expression of ds D g I and then sweep the transistor length from min L to min 10 L , the curve can be generated as following figure
Image of page 6
Page 7 of 12 Problem 10 1) is always inversely proportional to the channel length L 2) When the length L increase between min L and min 4 L , the drops most dramatically . Matlab and Cadence simulation Problem 2 Maltab sketch for GBW vs W/L We can see that, when W/L ratio = 979, we got the maximum GBW for 5.4775G The schematic used to verify this estimation: To ensure N7 always works in saturation region, I add a huge gain negative feedback to bias N7 dynamically. The SPECTRE simulation result is shown below:
Image of page 7

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

Page 8 of 12
Image of page 8