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Unformatted text preview: the resulting minimised form is: F = (W+Z').(W+Y').(W'+Y+Z).(W'+X'+Y).(X'+Y'+Z) The Sop from is preferrable, due to lesser number of gates needed.2) A significant hint in the question is the use of the circuit to check parity. The simplest parity checker is the XOR gate. the truth table of the XOR gate is: 0 0 0 0 1 1 1 0 1 1 1 0 Hence, the circuit can be thought of as checking for an odd number of 1s in the input consisting of 2 bits. To extend this idea to multiple inputs, just cascade a number od XOR gates. For 5 inputs, XOR the first 2 inputs, then XOR the output of this gate with the third input and so on. This however will produce an odd parity checker. Eventually, an Inverter must be used before the actual output can be observed. Alternatively, a truth table for 5 inputs can be constructed, and the circuit impemented using AND/Or gates....
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 Spring '08
 Ji
 Logic, Boolean Algebra, Summation, Karnaugh map, Canonical form

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