Sample_Final2_Ans

# Sample_Final2_Ans - COCO 1 A question about flip flops a A NAND latch is constructed as shown Each gate has a unit delay z Answers to Sample Exam 2

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COCO Answers to Sample Exam 2 1. A question about flip flops a. A NAND latch is constructed as shown. Each gate has a unit delay. y m z n Suppose m = n = y = 1 for a long time. Determine the steady-state value of z. z = 0. b. Given input waveforms m and n, determine the waveforms for y and z. m n y z = unit delay 1 1 1 1 0 0 0 0 No change c. Realize the functionality of a Toggle flip flop by designing an appropriate excitation network for a D flip flop. Fill in the next state and excitation table entries. T Q Q + D 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 d. Obtain a minimum expression for the input D. e. Draw the schematic for the network inside the dotted outer box. f. A negative-edge triggered JK Flip Flop with Set and Clear has a minimum Setup Time of 20 ns and a minimum Hold Time of 0 ns. Mark the minimum Setup-Hold Window about the appropriate Clocking Event. Computer Components and Operations Page 1 of 6 t q clock D C Q Q 20 ns 20 ns 20 ns 20 ns Clock min Setup- Hold Window

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2. A question about synthesizing a complex counter Synthesize a 3-bit binary counter that skips all the even numbers, i.e. follows the sequence: 1 3 5 7 1 ...
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## This homework help was uploaded on 04/22/2008 for the course ECSE 2610 taught by Professor Ji during the Spring '08 term at Rensselaer Polytechnic Institute.

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Sample_Final2_Ans - COCO 1 A question about flip flops a A NAND latch is constructed as shown Each gate has a unit delay z Answers to Sample Exam 2

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