Exam1soln - 3/5/02 55:138 Testing of Digital Logic Circuits...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 2
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 4
Background image of page 5
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 3/5/02 55:138 Testing of Digital Logic Circuits S.M.Reddy EXAM 1 Spring 2002 1) Determine the Collapsed set of single line stuck at faults in the circuit given below a) Using Fault Equivalence at a gate and b) Fault Equivalence and Fault Dominance Use the notation x/v, where x is the line name and v is the stuck at value 2) Find tests to detect the following faults in the circuit given using D-algorithm with 9 valued logic a) line 1 s-a—O b) line 18 s-a—l , Show all your work. ISCAS~89 benchmark Circuit 527 3) Using Deductive fault simulation determine which faults are detected by the test pattern shown at the output of gate 20. The faults of interest are {X6/O,7/1,8/1,8/0,l1/1,11/0,12/1,13/0,14/O,15/1,15/0,17/1,18/0,16/0,19/0}. You must show the lists associated with everyline. Representation: Output of gate 9 is line 9, gate 14 is line 14 and so on. LXI = kY'L’J‘” = 1’43 L‘5 ‘35 = L‘3A‘L7‘JE."‘—¥4A= Laldb V6 = Xé/O \\ 8 :\\5A 4451) Ulg/‘O x3, -. \n— mnfl/x = PM} :4 \6/01‘3/03 \JA =R1/C’7’ Lab=R3’/\31 MC‘: Lwfivlfle D U 357/0 x3 : mil MAUcY/o ‘C‘ng Lo‘ Aron/>5: : {Ag/(3 / \‘j/O { = -. 8 o if: L813; zip/.3: no —- mth \m 5 Lxg- \gfso “A :- :l.\\,o,=.\.H8 M2 : \ng Owe WM: [Cm/‘3 " WAG-mi) 4\ in : t\ossu¢:(a/.fi ANS. \Ul : Mob-U} U¢=2d ‘4 ’5 " \—\’L A has U‘B/ \5 Q‘B/I’jehmzbsb M6 5 \u 09 549.1; Ulé/o LCM/0?] : LsePr‘v‘UbR. it; = mow“ up :75 ‘1 <5} 63 s \ fl £6 4) Show all unique implications using 5 valued logic. a) s-a—O on line 24 b) s-a—l on line 24 « - A20 \&-O => Own: “1.21:; no -—> St 09 I) J 9' W H .4 \. I: I: 9 H V 3" H 0 \- °<3 H g 3-61.4 onfling :4“. ’— = 2‘ 314—) 0/ :> Acid jfllfl ,zgtyo :5 .U;_o > a; A) MW 212‘ '—“—> “40 =>A=o » a5=0 91:45:30 -\?~o :1) (Rasmx ,é=\ 21>)“ __ g]:\ \L...__ I _ ‘ ‘ i C 9 IE, If M nofi \Mp~9w& (my ; I 5) Find the Controllability with fanout correction and observability of each line in the circuit given below. ...
View Full Document

This test prep was uploaded on 04/22/2008 for the course EE 1 taught by Professor Dsd during the Fall '03 term at University of Iowa.

Page1 / 5

Exam1soln - 3/5/02 55:138 Testing of Digital Logic Circuits...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online