12 - 9-21-06COCO1SUPPLEMENTARY SLIDESon PLDs(Section

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Unformatted text preview: 9-21-06COCO1SUPPLEMENTARY SLIDESon PLDs(Section 6.3)9-21-06COCO2Implementing Larger Circuits: Programmable Logic ArraysOld technology: Buy chips with gates (e.g., a chip with 4 NAND gates), and wire them up to build logic circuitsmessy wiring, error pronetakes lots of space and powerNewer technology:Buy a single programmable logic array(PLA) chipCustomize this chip to implement our functionCan be as easy as downloading an espresso output to a PLA programmer.9-21-06COCO34 x 3 PLA(programable logic array) with six product terms.Note 4x2x6 + 6x3 fuses(nonvolatile memory cells).Implements sums of products.9-21-06COCO4But instead of many lines to the same AND gate, there is only one!There are pairs of input lines to each word (AND) line.If neither is connected, the input has no effect.If anyconnected line is Low, then word line is Lowand the output of the AND gate (and the input to any connected OR gate) is Low (0).Word lines are horizontal here.9-21-06COCO5Key to Efficiency:Reuse Shared Terms F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + AAAB' C'B' C'A BA B9-21-06COCO6Personality MatrixOutputsInputs Product t ermA 1 -1 -1 B 1 0 -0 -C -1 0 0 -F 0 0 0 0...
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This homework help was uploaded on 04/22/2008 for the course ECSE 2610 taught by Professor Ji during the Spring '08 term at Rensselaer Polytechnic Institute.

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12 - 9-21-06COCO1SUPPLEMENTARY SLIDESon PLDs(Section

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