chapt11_ComputerOrganization - From coupler-flange to...

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Unformatted text preview: From coupler-flange to spindle-guide I see Thy Hand. 0 God—- Predestlnotion in the stride o‘ yon connectin'—md. —R. Kipling introduction through 10. we examined the hmdamentsl principles of next, we will focus on applying l digital systems: the stored pm- In Chapters 1 digital design. In this chapter and the these techniques to one meior class 0 3mm computer. A stored program computer consists of a processing unit and an attached memory.r system. Commands that instruct the processor to per form certain operations are placed in the memory along with the data items to be operated on. The processing unit consists of dotapoth and control. The datapath contains registers to hold data and functional units, such an arithmetic logic units and shifters. to operate on data. The control unit is little more than a finite state machine that sequences through its states to [1} fetch the next instruction from memory. [2] decode the instruction to interpret its meaning. and (3) execute the instruction by moving andlor operating on data in the registers and functional units of the datepath. The critical design issues for one components together to mi number of control states to complete a typical operation. F a datapath are how to “wire” the vari- nimize hardware complexity and the or control. 11.1 Suumursulatiommtsr 51 [he issue is how to 0 anime th ' “mun” finite state lfihine- e relatively complex instruction Interpre- In . . I]de fittiochapter. we WI." discuss how hardware components are 0 computers. In addition, we will apply the techniquesrgr‘ e . l u ’ ‘ ‘ :8 e. apaths and pl‘UBESSOI COHth units. In I Point-la-polnt single-bus and ' I . , multiplevbus stmte ' ' m res r - :ata;l;{hf::r:lpfi:1:il:;s o):i the dotapotll. There is a Erode-fig 13:25:31 ‘ I on control com [exit . A path can simplify the control and \I'icepitersal.fr more complex dam. I The structure of the controller finite state machines state tilt]me The state diagram ice on to or . we will exploit in chapter 11:2, er control has a spectal structure that 11.1 Structure of a Computer F. 13:2: It: shows a high-level block diagram of a computer. it is de in o a central processing unit (CPU). or processor and:on attached memory a ystem. In turn. th - dalapflm and warm! mum a processor is decomposed into storfiiiféfig {also called the execution unit] contains registers for data “Ch u Shrine results and combinations] circuits for operating on sauna f a“ 1 mg: adding. and multiplying. The latter are somet' un tonal umts because they apply functions to data. Half: moved from memory into re gisters. [t is then moved 1 ' units. where the date manipulations take place. The recsutlltl: eh: Flinn “.1 Structure of a ptoeeseot. m =_1_.:._L____II_.I. ;_a_. _ ._.. . . f 5 . t i i 55! Chapter 1] Computer Organisation back into registers and eventually put back into memory. The datapath implements the pathways along which data can flow from registers to functional units and back again. The control unit (or instruction unit) implements a finite state machine that fetches a stream of instructions from memory. The instructions de- scribe what operations, such as ADD, should he applied to which operands. The operands can he found in particular registers or in memory locations. The control unit interprets or “executes” instructions by asserting the appropriate signals for manipulating the datapath. at the right time and in the correct sequence. For example. to add two registers and place [he results in a third register. the control unit {1) asserts the necessary con- Lro] signals to move the contents of the two source registers to the arith- metic logic unit [ALUL [2) instructs the ALU to perform an ADD operation by asserting the appropriate signals. and (3: moves the result to the specified destination register. again by asserting signals that estab- lish a path between the ALU and the register. Instructions can be grouped into three broad classes: data manipulation (add. subtract. etc.]. data staging {loadi'store dale fromIto memory}. and control (conditional and unconditional branches}. The latter class deter- mines the nexl instruction to fetch. sometimes conditionally based on in— puts lrom the datapath. For example. the instruction may be to take the branch if the last datapath operation resulted in a negative number. You are already familiar with the basic building blocks needed to im- plement the processor. You can interconnect NAND and NUR gates to build adder and logic circuits (Chapter 5} and registers (Chapters 6 and 7}. The processor control unit is iust another finite state machine {Chapters ti, 9. and ID). in the rest of this section, we will examine the components of a computer in a iittle more detail. as a prelude to the rest of this chapter. A processor control unit is considerably more complex than the kinds of finite state machines you have seen so far. A simple finite state machine is little more than next-state and output logic coupled to a state register. A control unit. on the other hand. needs access to its own datapath. a collection of registers containing information that affects the actions of the state machine. Program Countenflnslrnction Register For example. the control unit may have a register to hold the address of the next memory word to fetch for instruction interpretation. This is frequently called the program counter. or PC. when the instruction is moved from memory into the control unit. it must be held somewhere while the control decodes the kind of instruction it is. This staging memory, often implemented by a register. is called the instruction register or IR. It is a specislvpurpose register and is usually not visible to the assembly language programmer. “Kwanzdw w. . 11.1 Structure of a Computer 559 BIS-ll: States of the Bonlrol Unit The control unit can be in one of four basic phases: Reset. Fetch the Next instruction. Decode the instruction and Execute the Instruction. A high-level state diagram for a typical-con: trol unit is shown in Figure]1.2. Let‘s begin with the initialization seguence. An external reset signal places the finite state machine in its initial Reset state. from which the proceseor is initialized. Since the state of the processor contains more than just the state register of [he finite state machine. several of the special registers must also be sel to an initial value. For example. the PC must he set to some value. such as (1 before the first instruction can be fetched. Perhaps an accumulator regisler or a special register holding an indication of the condition of the riatapath will be set to I} as well. Although shown as a single stale in the figure. the ini- tialization process may be implemented by a sequence of states. Next. the machine enters the. Fetch Instruction state. The contents of the PC are sent as an address to the memory system. Then the control generates the signals needed to commence a memory read. When the operation is complete. d1e instruction is available on the mentorv's out- put euros and must be moved into the control unil's IR. Again. Fetch lnSlrUCiIQl‘lleDks like a single state in the figure. but Ihe actual imple— mentation Involves a sequence of states. I’l/d /—llfi< V I: \ Ream! ‘i ‘l—iliilialize I Machinn _ Fttltll] 'i lnstl‘. J! a. / “a Different .‘iuquoncu : c‘ for Each lltslnldim: /_ Load- ,‘fk\ \ TH)? . .1 , .I _ \ I \\ ./. \ Instr. It to—Raglsler 1_ 1mm. WIRE I _/ xx / Branch he.“ -" : Not Tisha“ 3‘ _ Branch i I" Inc-n II \ “K Figure 112 Hrgll-IEVEI control state diagram ———”—”—W 56: Chapter t1 Computer Organization tlprrutitnr .32 {.ItrtH .‘i Figure 11.3 Iterative (maceration oi :latapaih ubiects Clnce the instruction is available in the 1R. the control examines certain bits within the instruction to determine its type. Each instruction type leads to a different sequence of execution states. For example, the basic ax- ecution sequence for a ragistsr—to-zegister add instruction is identical to one for a register-to—regiater subtract. The operands must be moved to the ALU and the result directed to the correct register destination. The only differ once is the operation requested of the ALU. As long as the basic data move- ments are the same. the control sequences can be parametsrizad by the specific operation. decoded directly from the instruction. The state machine in the figure partitions the instructions into three classes: Branch. LoadIStore. and Register—to-Ragistar. Of course. there could be more classes. in the limit. there could be a unique execution sequence for each instruction in the processor’s instruction set. The final state takes care at housekeeping operations. such as incre- menting the PC. before branching back to fetch the next instrudion. The execution sequence for a taken branch modifies the PC itself. so it bypasses this step. The sequence of instruction fetch. execute. and PC increment continues until the machine is reset. While the details of the state diagram tnay vary from one instruction set to another. the general sequencing and the shape of the state diagram are generic to CPU state machines. The most distinguishing feature is the multiway decode branch between the instruction fetch and its axe- cution. This influences the design of controllers for simple CPUs that we describe in the next chapter. The elements of the datapath are built up in a hierarchical and iterative fashion. Consider how we go about constructing a 32-bit arithmetic unit for inclusion in the datapath. At the most primitive level. we begin with the half adder that can add 2 bits. By interconnecting two of these. we create the full adder. Once we have a single “bit slice" for the datapath obiect. we create as many instances of it as we need for the width of the datapath. For example. we construct a 32—bit adder of the ALU by itera- tiver composing 32 instances of a 1—bit—wide adder. As we saw in Chapter 5. an ALU bit slice is somewhat more compli- cated than this. It should also include hardware for logic operations and carry lookahead to perform arithmetic operations with reduced delay. The datapath symbol for a typical arithmetic logic unit is shown in Figure 11.3. The 32-bit A and B data inputs come from other sources in the datapath: the S output goes to a datapath destination. The operation signals come from the control unit: the carry—out signal is routed back to the control unit so that it may detect certain exceptional conditions. such as overflow. that may disrupt the normal sequencing of instruc- tions. We construct other datapath obiects. such as shifters. registers. and register files. in an analogous manner. (:untrol Fl {lulu Flor-.- fieure 11.4 Central ar'-"' data flows in a s-niple CPL'. raw 11 1 Structunaul a Computer 551 \ I . I . . julztfilgldtgél‘ with only a Single data register. usually called tho. (IL-Hum“— bI Ik . Is the Simplest machine organization. Figure 11.4 slum-r. alu- or. Lagram for such a Single accumulator machine. addlnslrutmons Ifor a single accumulator machine are called rim-I.- emIr-eIss JflSfl'ttCUUflS. This us because they contain nnlir a sinulu rial-or- I o tireinory. OneIoperant‘l is implicitly the M]: the other isoan {JIJl't'- a“ tit metndory. The Instructions are of the form A{‘ ‘= AC <opcr'ttion) emorv [A dress] <opemtion> co ‘ y I l I . old he " ‘ and so OIII ADD. SUBIRACI. AND. UR. Let S consider an ADD instruction. The Old value of the AC is replaced with the sum of the A05 c ‘ ontents' i , ; . . ,. location «t1 El the ( onlcttts of the specified memory Data and Cnntrnl Flows Figure 11.4 shows the flow of riots and control between memory. the control registers (IR. MAR. and PC: the data rtggter {AC}. and the functional units tALUJ. The MAR is the Memory . ems Register. a storage element that holds the address during mani‘ Lil‘\r ti . . '56:. Da a f 0W? alr‘. S town as lat] C at: wail ‘ l'lt" (ltl‘ter line I l . l l i ' ' 0 ll ' - I I [I I 1119.5. l . 5 PIC (xx: oi tlIiIe datapath consists of the ariLtinietic logic unit and the .. e .. is t c source or destination of all transfers. These transfers Start! Path ' I I ' u-HLL‘tKl T’Illtl I at: ' h : W... I l I _, x J—-\ ._ ‘1 .I ,' H I" \_I I . II; : Molnar-i \ \ I/ ,l hits with: l —‘ / l' I I M u'uttls t-‘sv. l ALL! I - a ._ I'— I _ —.—" . . 1—1— , I Upliulfi l c‘ u : —: - i : ' —— a |:l:t|l‘lir:il(lll |’|||.'t m— 562 Chapter 11 Computer Organization are initiated by store, arithmetic. or load operations. Let's look at them in more detail. - The instruction identifies not only the operation to be performed but also the address of the memory operand. Store operations move Ihe contents of the AC to a memory location specified by bits within the in- struction. The sequencing begins by moving the specified address from the [R to the MAR. Then the contents of the AC are placed on the memory’s data input lines while the MAR is placed onto its address lines. Finally. the memory control signals are cycled through a write sequence. Arithmetic operations take as operands the contents of Ihe accumula- tor and the memory location specified in the instruction. Again. the con- trol moves the operand address from the IR [0 the MAR, but this time it invokes a memory read cycle. Data obtained from the load path is com- bined with the current contents of the AC to form the operation result. The result is then written back to the accumulator. A load operation is actually a degenerate case of a normal arithmetic operation. The control obtains the B operand along the load path from memory. it places the ALU in a passvthmugh mode. and it stores the result in the AC. Whereas loadlstore and arithmetic instructions manipulate the AC, branch instructions use the PC. If the instruction is an unconditional branch. the address portion of the IR replaces the PC. changing the next instruction to be executed. Similarly. a conditional branch replaces the PC it a condition specified in the instruction evaluates to true. Placement 0! Instructions Ind Dell There are two possible ways to con- nacl the memory system to the CPU. The first is the so-called Princeton architecture instructions and data are mixed in the same memory. in this case. the instruction and loadlstore paths are the same. The alternative is die Harvard architecture. Data and instructions are stored in separate memories with independent paths into the processor. The Princeton architecture is conceptually simpler and requires less connections to the memory. but the Harvard architecture has certain perfor- mance advantages. A Harvard architecture can fetch the next instruction even while executing the current instruction. If the current instruction needs to access memory to obtain an operand. the next instruction can still be moved into the processor. This strategy is called instruction prefetching, because the instruction is obtained before it is really needed. A Princeton architecture can prefetch instructions too. It is just more complicated to do so. To keep the discussion simple. we will assume a straightforward Prince— ton architecture in the rest of this chapter. Betailed Instruction Trace As an example of the control signal and data flows needed to implement an instruction. let‘s trace a simple instruc— tion that adds the contents of a specified memory location to the AC.- 3. The control moves the o rand add ' ' second memory read opergfion to fetcffhebhiei‘lgfl.“ MAR and hang a 4. Once the data is availabl drives the ALU with si to form the 5 result. a memory along “18 load path. the control gnals instructing it to ADD its A and B operands s. The control then moves the S tion ofthe instruction. ii. The control increments th I 9 program counter to i ' tron. The machine returns to the first step. W m m the as“ msmu‘ result into the AC to complete the execu- I . most of what the Con— from one register to anothe . asserting the appro priate control signals at the ' correct t1 . commonly described in term mes comm] sequencas am Instruction Patch 3:; Mime] Move PC to MAR ory ea : ' Memory ‘6 LR: Assert Memory READ signal Lead IR from Memory Instruan Decode: IF IR<op code) = ADD_FROM_MEMURY THEN Instruction Execution: IR<address bita> —> MAR: Memory Read; Memory —9 ALU B: Move operand address to MAR Assert Memory READ signal Gate Memory to ALU H :EU—iASEU A; Gate AC to ALU A : lnstru t AL ALU S q AC: I: U to perform ADD Gate ALU result to AC PC in ‘ crement, Instruct PC to increment 5M Chauler 11 Bummer Urganiiation I"; - -——-v M I A ' Ilt _ Ii [inquest Reuth'Wrilu Memory Whil I.L}-‘h"t' Dal-u q—i— M It —" Il:.~ilr|ll:l1'l:|l.|i It 4—— Fimue 11.5 MEIIIOI’Y interime. We WI‘HU the [Ile'al'lUll stuluments in terms of the mantra] signals to he asserted. such as Mammy Hmld. ALU ADD. or PC increment, WE! write leglster-lu-reglslur transient: in the form soumfl. mgl'slel' -; destination mg- Ester. The detailed pathways IJelwcl-ln registers determine tho more pull (all mgister trmlsfer descriplion. We will 500 more register transfer clustiip— firms in Secliul] 11.2. Figure. 11.4 showed a masonnhly generic illtert'aw to memory. A more real- istit: Vii-cw for a Princeton archiluclurlz machine is shown in Figure 11.5. The key elements are the two Special registers. MAR’and MBR, and Illa {luau control signals. Request. Readel'iIL‘. . and Wait. Lot's starl with the registers. We have seen the MAR before. in Figure 11.5. it L:an be loaded from llll: pmgral‘n counter for inslrueliuu fetch 01' from the [R with a load (11' slum address. To {tacoupln the memory from the internal working at the processor. wl'l l'mrmlune ll s nl:l interface register. the Martial? Bufl'el' Register. or MBR. A bidlrucllmml path [ui' ioadfslm'e duh] exists between Ihe processor Llulupulll llnd the MB“. while the pathway for instructions helweul‘l ttlu Mtilt and IR is unidirl. tinnal. Besides the address unci (Intu lines. the lnlert'aue In memory :iuns'lsts ol' Illl'OE control signals. ‘I'he Requesl signal notifies the memory [hat the plain-«Hem wishes to amass: it. The RUEIKUWI'liF. signal sliclufies the din-ll:- Iiml: mull from memory (in {I load illlll write to memory on a store. 'l'hc Wall signal leis monum- tall the processor. in offal mllt'ying the pro— trllssnl‘ Ihat its mulnl Ilnst has not yet been serwued. We can think of Wail as the 1::Jl11plement of un ucknowledgmanl signal. Prncassor-Mnmnry Handshnking In their most general Form. Kha manner}. system amt the processor [In llUl shall'e a1 conmlon clock. Ti} 9m:le proper lrunslor of data. we should Follow the filllli‘U}"Clfi signaling convention 0‘: Section 6.5.2. Thu prumssm' :lsserts the readfwrite diruclil‘m. places data in the MAR [and the MBR if a write}. :11ch asserts ltoqunst. Thu memur) lloruullly asserts W . luulsscrling it when lhu mart nl- wrllu is cumplule. When the processor lmti :5 that Wall is [10 longer a‘m'ted. :il Latches llatal lulu [he MtiR on ll l‘e'dll or tl'i-sl-Ites the delta conm. . on to lllt-Elllul'} on a writs. The procussor unasserts its Requesl line and must wall in:- the Walt signal to he renssurlelt by the Memory before it can issue it.» next memory request. 'l‘lm signaling t-l’tl\-'Uft][‘l11$ are shown in Figure 11.6. 't‘he l'IJLlr-ct'liil handshake of [he léoqllnst and Walt signals for the lead sequence wall- as follows: (Ii-(rill l: liraquclst asserted. Read data placed on mummy data bus. f..'_'. It! 2: \"J'alt LliiitcitiUl‘lL'lL'l. Cl’l! latches l‘ualtl Llala illtu MHR. 11 1 Structure at a Computer 505 *Jm—_\__fi_\_ /— ' fix HeadIWrilu —..- ~—.—._ . Dull! ——( T-‘rom Mmlmry >—<.‘ 'ltJ Admin-SJ; Wu H _ .. \_¢ ‘I_/ Figure 11.6 Mammy internals timing wavelurms. Cyclfi 3: Request unasnartcd. Cycle 4: Wait HSSOI'IL‘d. In this signaling convention. a new requesl can be made only after Ilie Wait signal is asserted, 'l‘ho write uynln is analogous. Figure 11.? shows possible slate mauhins fi'agmeuls for implementing the tour-cycle handshake with memory. We assume a Monro machine...
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