This preview shows page 1. Sign up to view the full content.
Unformatted text preview: de 1 VHDL-Very high speed Hardware Description Language Using VHDL, you can design, simulate, and synthesize a digital circuit. The VHDL design ow includes: block diagram, coding, compilation, simulation, and synthesis. Synthesis is concerned with loading the compiled codes into the chip such as a PLD and verifying the performance of the design in an actual circuit in terms of functional and timing performance. VHDL entity declaration Slide 3
architecture definition VHDL Program Structure
It consists of two parts: entity declaration and architecture de nition. Entity de nes a module's name, its input and output. Architecture de nition describes the module's function. de 2 Slide 4 The name of all VHDL programs should end with an extension .vhd such as mydesign.vhd . VHDL Program Structure: Entity
The syntax for a VHDL entity consists of entity name, input and output variable names, types, modes.
Table 4-27 Syntax of a VHDL entity declaration.
entity entity-name is port signal-names : mode signal-type; ( signal-names : mode signal-type; ... signal-names : mode signal-type); end entity-name; de 5 Slide 7 Entity De nition Examples
Entity de nitions for XOR gate, BUT-NOT gate, D-FF, etc.. Entity and signal name-a string of characters
(containing no spaces and hyphens) type-for VHDL prede ned types
bit bit_vector boolean character integer real VHDL operators
Table 4-30 Predefined operators for VHDL's integer and boolean types.
Operators integer Operators boolean Ta severity_levelb l e 4 - 2 9 VHDL predefined string time types. + * / mod rem abs ** de 6 Often, we use std logic and std logic vector for bit and bit vector. Slide 8 addition subtraction multiplication division modulo division modulo remainder absolute value exponentiation and AND OR or nand NAND nor NOR xor Exclusive OR xnor Exclusive NOR not complementation mode-in, out, bu er, inout, In addition, there are also relational operators: =, = =, <, <=, >, and >=. de 9 Note: 1) results of Boolean and Relational operations are all Boolean data type. 2)<= can also be used as the assignment operator. Slide 11 VHDL IF statement if boolean-expression then sequential-statement end if; Table 4-57 Syntax of a VHDL if statement. e 10 Syntax statement WHEN boolean-expression ELSE statement An example z <= `0' WHEN x = = 1 else z <= `1' VHDL WHEN statement if boolean-expression then sequential-statement else sequential-statement end if; Slide 12 elsif boolean-expression ... if boolean-expression then sequential-statement then sequential-statement elsif boolean-expression then sequential-statement end if; if boolean-expression then sequential-statement elsif boolean-expression then sequential-statement ... elsif boolean-expression then sequential-statement else sequential-statement end if; A Simple VHDL Program
Table 4-58 architecture prime7_arch of prime is Prime-numberbegin detector architecture process(N) using an if statement. variable NI: INTEGER; begin NI := CONV_INTEGER(N); if NI=1 or NI=2 then F <= '1'; elsif NI=3 or NI=5 or NI=7 or NI=11 or NI=13 then F <= '1'; else F <= '0'; end if; end process; end prime7_arch; Ta bl entity Inhibit is -- also known as 'BUT-NOT' e 4 - 2 6 port (X,Y: in BIT; -- as in 'X but notVHDL program for Y' Z: out BIT); -- (see [Klir, 1972]) "inhibit" gate. an end Inhibit;
architecture Inhibit_arch of Inhibit is begin Z <= '1' when X='1' and Y='0' else '0'; end Inhibit_arch; e 13 Slide 15 Note: 1)use two hyphens to indicate the start of comments. 2)reserved words such as entity, port, is, in, out, bit are not case sensitive. VHDL Program Structure: Architecture
The VHDL architecture template
architecture architecture-name of entity-name is type declarations signal declarations constant declarations function definitions procedure definitions component declarations begin concurrent-statement ... concurrent-statement end architecture-name; e 14 Ta bl e 4 - 2 8 Syntax of a VHDL architecture definition. WITH Statement
Table 4-52 Syntax of VHDL selected signalassignment statement.
with expression select signal-name <= signal-value when choices, signal-value when choices, ... signal-value when choices; Slide 16 An example e 17 Table 4-53 Prime-number detector architecture using selected signal assignment. architecture prime4_arch of prime is begin with N select F <= '1' when "0001", '1' when "0010", '1' when "0011" | "0101" | "0111", '1' when "1011" | "1101", '0' when others; end prime4_arch; Slide 19 WHEN OTHERS => Z <= `0' END CASE e 18 Syntax: CASE expression IS WHEN choices => statements WHEN choices => statements END CASE Example: CASE state IS WHEN S1 => Z <= `1' WHEN S2 => Z <= `2' CASE Statement VHDL Loop
for identifier in range loop sequential-statement ... sequential-statement end loop; Table 4-62 Syntax of a VHDL for loop. An example Table 4-63 library IEEE; Prime-numberuse IEEE.std_logic_1164.all; detector architecture using a forstatement. entity prime9 is port ( N: in STD_LOGIC_VECTOR (15 downto 0); F: out STD_LOGIC ); end prime9;
architecture prime9_arch of prime9 is begin process(N) variable NI: INTEGER; variable prime: boolean; begin NI := CONV_INTEGER(N); prime := true; if NI=1 or NI=2 then null; -- take care of boundary cases else for i in 2 to 253 loop if NI mod i = 0 then prime := false; exit; end if; end loop; end if; if prime then F <= '1'; else F <= '0'; end if; end process; end prime9_arch; VHDL Implementation of Decoders
X: bit vector (2 down 0) means X is an array of 3 bits. its element is indexed from 2 to 0, with X 2] for the MSB and X 0] for the LSB. X: bit vector (0 down 2) means X is an array of 3 bits. its element is indexed from 0 to 2, with X 0] for the MSB and X 2] for the LSB. e 21 T a b l e 5 - 1 5 Dataflow-style VHDL program for a 74x138-like 3-to-8 binary decoder.
library IEEE; use IEEE.std_logic_1164.all; entity V74x138 is port (G1, G2A_L, G2B_L: in STD_LOGIC; A: in STD_LOGIC_VECTOR (2 downto 0); Y_L: out STD_LOGIC_VECTOR (0 to 7) ); end V74x138; e 22 Note: always include ieee.std logic 1164.all in the beginning of a VHDL program. -- enable inputs -- select inputs -- decoded outputs Slide 24 architecture V74x138_a of V74x138 is signal Y_L_i: STD_LOGIC_VECTOR (0 to 7); begin with A select Y_L_i <= "01111111" when "000", "10111111" when "001", "11011111" when "010", "11101111" when "011", "11110111" when "100", "11111011" when "101", "11111101" when "110", "11111110" when "111", "11111111" when others; Y_L <= Y_L_i when (G1 and not G2A_L and not G2B_L)='1' else "11111111"; end V74x138_a; Ta bl e 5 - 4 3 Behavioral architecture for a 4-input, 8-bit multiplexer.
architecture mux4in8p of mux4in8b is begin process(S, A, B, C, D) begin case S is when "00" => Y <= A; when "01" => Y <= B; when "10" => Y <= C; when "11" => Y <= D; when others => Y <= (others => 'U'); end case; end process; end mux4in8p; e 25 Multiplexers in VHDL Slide 27 -- 8-bit vector of 'U' Ta bl e 5 - 4 2 Dataflow VHDL program for a 4-input, 8-bit multiplexer.
library IEEE; use IEEE.std_logic_1164.all; entity mux4in8b is port ( S: in STD_LOGIC_VECTOR (1 downto 0); -- Select inputs, 0-3 ==> A-D A, B, C, D: in STD_LOGIC_VECTOR (1 to 8); -- Data bus input Y: out STD_LOGIC_VECTOR (1 to 8) -- Data bus output ); end mux4in8b; e 26 Slide 28 architecture mux4in8b of mux4in8b is begin with S select Y <= A when "00", B when "01", C when "10", D when "11", (others => 'U') when others; -- this creates an 8-bit vector of 'U' end mux4in8b; Syntax: SUBTYPE subtype-name IS type-name (start to end) CONSTANT constant-name: subtype-name : = value Example: SUBTYPE state IS STD LOGIC VECTOR (1 to 3) CONSTANT S0: state :=\000" CONSTANT S1: state :=\001" CONSTANT S2: state :=\011" CONSTANT S3: state :=\010" SUBTYPE Statement architecture Inhibit_archf of Inhibit is function ButNot (A, B: bit) return bit is begin if B = '0' then return A; else return '0'; end if; end ButNot; begin Z <= ButNot(X,Y); end Inhibit_archf; Ta bl e 4 - 3 6 VHDL program for an "inhibit" function. e 29 CONSTANT S4: state :=\110" These statements can be used to relate the states's mnemonic names to their binary assignment. Slide 31 e 30 Like functions for high level programming language (e.g. C++), a VHDL function has its input arguments and returns a result of certain type. Syntax for VHDL functions VHDL Functions Slide 32 A process is a collection of statements de ned in an enclosing architecture. A process statement is introduced by the keyword process. Syntax: PROCESS (signal-name, signal-name, signal-name) type declarations variable declarations constant declarations BEGIN statements PROCESS Statement Table 4-63 library IEEE; Prime-numberuse IEEE.std_logic_1164.all; detector architecture using a forstatement. entity prime9 is port ( N: in STD_LOGIC_VECTOR (15 downto 0); F: out STD_LOGIC ); end prime9; e 33 statements ... END PROCESS Slide 35 architecture prime9_arch of prime9 is begin process(N) variable NI: INTEGER; variable prime: boolean; begin NI := CONV_INTEGER(N); prime := true; if NI=1 or NI=2 then null; -- take care of boundary cases else for i in 2 to 253 loop if NI mod i = 0 then prime := false; exit; end if; end loop; end if; if prime then F <= '1'; else F <= '0'; end if; end process; end prime9_arch; e 34 PROCESS Example Slide 36 ENTITY vending machine IS port (CLOCK,A,B: in std logic Z: OUT std logic) END ARCHITECTURE vending arch OF vending machine IS PROCESS (CLOCK) BEGIN IF CLOCK' event and CLOCK='1' then Another PROCESS Example e 37 CASE state IS WHEN S1 => Z<='1' WHEN S2 => Z <='2' WHEN OTHERS => Z <= '0' END CASE END IF END PROCESS END vending arch e 38 Design a clocked synchronous state machine with Two inputs, A and B, and a single output Z that is 1 if: A had the same value at each of the two previous clock ticks, or B has been 1 since the last time that the rst condition was true. Otherwise, Z is 0 1) derive the transition/output table 2) implement the table in VHDL (see section 7.12) VHDL for State Machine ...
View Full Document
This homework help was uploaded on 04/22/2008 for the course ECSE 2610 taught by Professor Ji during the Spring '08 term at Rensselaer Polytechnic Institute.
- Spring '08