NanoCompAssyLang

NanoCompAssyLang - 4/7/08 Description of the NanoComp...

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4/7/08 1 Description of the NanoComp Instruction Set Registers, memory, and & elds Memory Processor state PC 7..0 : program counter (address of next instruction) IR 7..0 : instruction register Run: one bit run/halt indicator Strt: start signal R[0. .3] 7 ..0 : general purpose registers Main memory state Mem[0. .2 3 - 1] 7..0 : 256 addressable bytes of memory Formats Instruction formats IR 7..4 : operation code field Rx 1..0 := IR 3..2 : Rx field Ry 1..0 := IR 1..0 : Ry field Cond 3..0 := IR 3..0 : branch condition Instruction interpretation (instruction_interpretation := ( Run Strt Run 1; PC 0; initialize the PC to M[0] Run (IR M[PC]: PC PC + 1; instruction_execution):
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2 The NanoComp Instruction set Notes: Cond is the four lsbs of the instruction. The four bits are Z, N, C, and V respec- tively. Cond will be ORed with the contents of the & ags register. If the result is not zero, cond is true.
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This note was uploaded on 04/21/2008 for the course ECEN 5120 taught by Professor Hagan,mart during the Spring '08 term at Colorado.

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NanoCompAssyLang - 4/7/08 Description of the NanoComp...

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