Lecture (10) - Computers Organization CEXXX Lecture#10...

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Computers Organization تاموظنم بساحلا CEXXX
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Lecture #10
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Chapter 4 The Processor
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Chapter 4 — The Processor — 4 Pipelining Analogy Pipelined laundry: overlapping execution Parallelism improves performance § 4 . 5 A n O v e r v i e w o f P i p e l i n i n g Four loads: Speedup = 8/3.5 = 2.3 Non-stop: Speedup = 2n/(0.5n + 1.5) ≈ 4 = number of stages
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Chapter 4 — The Processor — 5 MIPS Pipeline Five stages, one step per stage 1. IF: Instruction fetch from memory 2. ID: Instruction decode & register read 3. EX: Execute operation or calculate address 4. MEM: Access memory operand 5. WB: Write result back to register
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Chapter 4 — The Processor — 6 Hazards Situations that prevent starting the next instruction in the next cycle Structure hazards A required resource is busy Data hazard Need to wait for previous instruction to complete its data read/write Control hazard Deciding on control action depends on previous instruction
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Chapter 4 — The Processor — 7 Multi-Cycle Pipeline Diagram Form showing resource usage
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Chapter 4 — The Processor — 8 Single-Cycle Pipeline Diagram State of pipeline in a given cycle
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Chapter 4 — The Processor — 9 Datapath with Forwarding
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Chapter 4 — The Processor — 10 Datapath with Hazard Detection
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