EE101Lecture17

EE101Lecture17 - Introduction to Digital Logic Lecture 17:...

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© Mark Redekopp, All rights reserved Introduction to Digital Logic Lecture 17: Sequential Logic Bistables Latches
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© Mark Redekopp, All rights reserved Bistables • Cross-Connected NOR gates form a valid bistable (in this case an SR bistable) • When Set = 1, output forced to 1 • When Reset = 1, output forced to 0 • When both are 0, Q at its present value 0 (illegal) 0 (illegal) 1 1 1 0 1 0 0 1 0 1 Q 0 Q 0 0 0 Q Q R S R S Q Q
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© Mark Redekopp, All rights reserved Bistable • A bistable with active-lo inputs can be built with cross-connected NAND gates 1 (illegal) 1 (illegal) 0 0 1 0 0 1 0 1 1 0 Q 0 Q 0 1 1 Q Q R S = Notice the active-lo inputs (A 0 on S, sets Q=1) To “view” it as active- lo we can redraw our NAND gates S R Q Q S R Q Q
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© Mark Redekopp, All rights reserved Criteria for a Bistable 1. Able to set (preset) => Force Q=1 2. Able to reset (clear) => Force Q=0 3. Able to remember (hold) => Q = Q 0
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© Mark Redekopp, All rights reserved Checking for Bistable Validity • Need to check the 3 criteria – Can it set, reset, remember • Method for checking: – Find the passive input values of bistable inputs (the values that allow Q to cycle around the cross- connected loop) • Those passive input values identify the inactive values of the inputs…thus we can know whether the inputs are active hi or low – Activate each input separately to find if it is the Set or Reset input • Just see what happens to Q when you activate each input separately
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© Mark Redekopp, All rights reserved Problem w/ Bistables • Bistables will remember input values whether we
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EE101Lecture17 - Introduction to Digital Logic Lecture 17:...

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