Experiment1

Experiment1 - Experiment #1 CPE 269 04 Professor Bell Oct....

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Experiment #1 CPE 269 – 04 Professor Bell Oct. 3, 2006 Colin McKinney Jon Lyons
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Structural VHDL: entity exp1_ckt is Port ( CLK_IN : in STD_LOGIC; RESET_IN : in STD_LOGIC; UP_IN : in STD_LOGIC; DEN1 : in STD_LOGIC; DEN 2 : in STD_LOGIC; CKT_OUT : out STD_LOGIC_VECTOR (7 downto 0)); end exp1_ckt; architecture ckt of exp1_ckt is component bit_3_count port (CLK, RESET, UP : in STD_LOGIC; COUNT : out STD_LOGIC_VECTOR(2 downto 0)); end component; component decoder port (DEN : in STD_LOGIC; D_IN : in STD_LOGIC_VECTOR(2 downto 0); F_OUT : out STD_LOGIC VECTOR(7 downto 0)); end component; signal count_to_decoder : STD_LOGIC_VECTOR( 2 downto 0); signal d_nand : STD_LOGIC; begin d_nand <= not (DEN1 and DEN2); x1 : bit_3_count port map (CLK => CLK_IN, RESET => RESET_IN, UP => UP_IN, COUNT => count_to_decoder); a1 : decoder port map (DEN => d_nand, D_IN => count_to_decoder, F_OUT => CKT_OUT); end ckt;
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Explanation of Circuit (Part 7 of procedure): The circuit outputs minterms is an ascending order if the UP, DEN1, and DEN2 inputs are high and the RESET input is low. This is triggered by the rising edge of the CLK
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This note was uploaded on 04/25/2008 for the course CPE 269 taught by Professor Bell during the Spring '06 term at Cal Poly.

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Experiment1 - Experiment #1 CPE 269 04 Professor Bell Oct....

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