# Lab 2 - Lab 2 CPE 269 Oct 10 2006 Jonathan Lyons Colin McKinney Bench#14 Description of Circuit Function The circuit has 4 inputs(CLK HOLD UP_DOWN

This preview shows pages 1–3. Sign up to view the full content.

Lab 2 CPE 269 Oct. 10, 2006 Jonathan Lyons Colin McKinney Bench #14

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Description of Circuit Function: The circuit has 4 inputs (CLK, HOLD, UP_DOWN, and CLR). If the CLR input is high, the 4-state one hot encoded FSM resets to ‘0001’. If HOLD is high, the FSM will hold its current state. If CLR is ‘low’ and the clock hits a rising edge, the FSM will count up in one-hot states up to ‘1000’ and then start again at ‘0001’ on the next rising edge. If the UP_DOWN signal is low, then the FSM counts down in one-hot states. The output Z is dependent on the state of the FSM. The output RCO is ‘high’ when the FSM is in the state S3 (“1000”). Questions: 1) System Clock Frequency = 50MHz = 50 x 10^6 Hz Fast_clk = system clock frequency / 2^12 = 50x10^6 / 2^12 = 12,207 Hz Slow_clk = system frequency / 2^25 = 50x10^6 / 2^25 = 1.49 Hz Period = T = 1/F => Fast_clk T = 1 / 12,207 Hz = 8.19 x 10^-5 s Slow_clk T = 1 / 1.49 Hz = 0.67 s 2) We cannot simulate the entire circuit because the clock divider circuit slows the
This is the end of the preview. Sign up to access the rest of the document.

## This note was uploaded on 04/25/2008 for the course CPE 269 taught by Professor Bell during the Spring '06 term at Cal Poly.

### Page1 / 3

Lab 2 - Lab 2 CPE 269 Oct 10 2006 Jonathan Lyons Colin McKinney Bench#14 Description of Circuit Function The circuit has 4 inputs(CLK HOLD UP_DOWN

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online