exp0VHDL - Experiment 0 Introduction to Laboratory Hardware...

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Experiment 0 - Introduction to Laboratory Hardware, the Xilinx ISE Software, and VHDL Dataflow and Behavioral Modeling CPE 269 – 04 Prof. Bell 9/27/2006 Colin McKinney John ?
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Purpose This Laboratory experiment will serve as an introduction to the laboratory hardware used during the quarter in CPE-269. The main goals include becoming familiar with the Digilab XCRP board, an introduction to the Xilinx ISE software, reviewing the Xilinx circuit design and implementation methodology, and an introduction to VHDL modeling concepts. Also, learning how to implement simple digital circuits using both dataflow and behavioral modeling will be stressed in this lab. Section 1 In this section we were instructed to design a three input NAND Gate using VHDL in both Data Flow and Behavioral coding styles. A copy of our code follows: A. Data Flow library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity exp0a is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; F : out STD_LOGIC); end exp0a; architecture Behavioral of exp0a is begin F <= NOT(A AND B AND C); end Behavioral; B. Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity exp0a is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; F : out STD_LOGIC); end exp0a; architecture Behavioral of exp0a is begin F <= '0' when (A AND B AND C) else '1'; end Behavioral;
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We were also asked to use the Benchmark utility to test and simulate our code with ModelSim, but we had problems with the Licensing of the software. This created a large amount of wasted time and effort, and was never able to be resolved. We encountered a similar problem regarding the creation of a constraints file to
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This note was uploaded on 04/25/2008 for the course CPE 269 taught by Professor Bell during the Spring '06 term at Cal Poly.

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exp0VHDL - Experiment 0 Introduction to Laboratory Hardware...

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