2 - ds747_axi_intc - LogiCORE IP AXI INTC(v1.01a DS747...

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DS747 June 22, 2011 1 Product Specification © Copyright 2010-2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. AMBA is a trademark of ARM in the EU and other countries. Introduction The LogiCORE™ IP AXI Interrupt Controller (AXI INTC) core concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor. The registers used for checking, enabling, and acknowledging interrupts are accessed through a slave interface for the AMBA ® protocol’s AXI (Advanced Micro controller Bus Architecture Advanced eXtensible Interface) specification. The number of interrupts and other aspects can be tailored to the target system. This AXI INTC core is designed to interface with the AXI4-Lite protocol. Features AXI interface is based on the AXI4-Lite specification Configurable number of (up to 32) interrupt inputs Single interrupt output Easily cascaded to provide additional interrupt inputs Priority between interrupt requests is determined by vector position. The least significant bit (LSB, in this case bit 0) has the highest priority Interrupt Enable Register for selectively enabling individual interrupt inputs Master Enable Register for enabling interrupt request output Each input is configurable for edge or level sensitivity: Edge sensitivity can be configured for rising or falling Level sensitivity can be active High or active Low Automatic edge synchronization when inputs are configured for edge sensitivity Output interrupt request pin is configurable for edge or level generation: Edge generation configurable for rising or falling Level generation configurable for active High or active Low LogiCORE IP AXI INTC (v1.01a) DS747 June 22, 2011 Product Specification LogiCORE IP Facts Table Core Specifics Supported Device Family (1) Artix-7 (2) , Virtex-7, Kintex-7 Spartan-6 (3) , Virtex-6 (4) Supported User Interfaces AXI4-Lite Resources Frequency LUTs FFs DSP Slices Block RAMs Max. Freq. Refer to Table 13 through Table 17 Provided with Core Documentation Product Specification Design Files VHDL Example Design Not Provided Test Bench Not Provided Constraints File None Simulation Model None Tested Design Tools Design Entry Tools ISE 13.2 Simulation Mentor Graphics ModelSim (5) Synthesis Tools XST 13.2 Support Provided by Xilinx, Inc. Notes: 1. For a complete list of supported derivative devices, please see the IDS Embedded Edition Derivative Device Support . 2. For more information on 7 series devices, see the 7 Series FPGAs Overview [Ref 3] 3. For more information on Spartan®-6 devices, see the Spartan-6 Family Overview [Ref 4] 4. For more information on Virtex®-6 devices, see the Virtex-6 Family Overview [Ref 5] .
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  • Fall '16
  • Interrupt, Interrupt request, Programmable Interrupt Controller, Axi, AXI INTC

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