ECE 394 - Experiment 6

# ECE 394 - Experiment 6 - 1 Introduction The main purpose of...

• Lab Report
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1. Introduction: The main purpose of this experiment is to learn how to design one of the most frequently used sequential circuit components, Counters. Almost all computer and digital electronic devices use counters to execute a predetermined sequence of states on applying a series of input pulses. For instance, binary counters are designed to execute a sequence of 2 N states, where N represents the number of flip-flops used to recognize all states. There are two methods of designing Counter circuits, which divide the Counters on the market into 2 major categories: Asynchronous Counters operate by toggling the value stored in a flip-flop between 0 and 1 using the transition of the previous flip-flop’s output as a clock input. Since each flip-flop receives its clock from the output of the previous flip-flop, the output bits will ripple until the last flip-flop gets the turn to output its correct output. Flip-flops have nonzero propagation delay; thus, these counters are relatively slow and the delay builds up as the number of flip-flops increase. Synchronous Counters get rid of the rippling phenomenon in Asynchronous counters along with the cumulative propagation delay issue. Instead, every flip-flop receives a separate connection to the master clock signal input and extra logic gates, namely AND- gates, are used to control the sequence of the counter’s states. The Synchronous Counter used for this experiment, displayed in Figure 3 below, is also known as a parallel counter because the J-K inputs are applied in a parallel fashion. It is important to observe that in such a parallel scheme the number of inputs to each AND gate increases linearly with the number of stages. After finishing this lab, students should have successfully accomplished the following objectives: Objectives: Understand the basic structure of Counters and learn about the various types of counters on the market Implement 4 – bit Asynchronous Up and Down Ripple Counters and observe their performance and speed limitations. Build 4 – bit Synchronous Up and Down Counters and compare their performance to their counterpart ripple counters. Equipment: Protoboard 2 J – K Flip-Flops (74LS76) 1 3-input AND (7411) 5 LEDs (4 for the outputs and 1 for the clock cycle) 5 resistors 1 | P a g e

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2. Procedure: PART I – ASYNCHRONOUS RIPPLE UP – COUNTER 1. Find 2 J – K Flip-Flops – 74LS76 chip, 5 LEDs (4 for the outputs L1-L4 and 1 for the CLK input) and a switch in your electronics kit and use them to built the Asynchronous Counter-up ripple counter in Figure 1. Note that the 74LS76 chip pin configuration schematic is attached in Figure 2 below.
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• Fall '15
• counter circuit

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