lec11_clock_dist_design

lec11_clock_dist_design - Clock Distribution Design Ref...

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Clock Distribution II Clock Distribution Design Ref: Circuits, Interconnections and Packaging of VLSI, H. B. Bakoglu, Addison Wessley (Out of Print) Digital Signal Integrity, Brian Young, Prentice Hall, ISBN 0-13-028904-3
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Clock Distribution II Common Clock – Non-ideal Effects Common Clock – Non-ideal Effects in m jitter clock TOF p H in m jitter clock TOF S p t t t t TOF t t t t t t t TOF t f arg arg max 1 + + + + + < + + + + + + < Uncertainty in the arrival time of a signal is called as the skew Clock skew can occur due to many sources • Clock jitter t jitter occurs due to variation in the clock generator output • This results in an uncertainty t clock in the clock period • Unbalanced interconnections cause clock skew t TOF • Power supply noise, cross talk and reflections cause clock skew t margin δ = sum total of all the non-ideal effects
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Clock Distribution II Skew due to Variable Length Skew due to Variable Length
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Clock Distribution II HW 4: Problem 5 HW 4: Problem 5
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