lec5_interconnect_resistance_RC_Delay

lec5_interconnect_resistance_RC_Delay - Interconnect...

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Interconnect Ref: Circuits, Interconnections and Packaging of VLSI, H. B. Bakoglu, Addison Wessley (Out of Print)
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Delay due to Interconnect Resistance int int % 50 7 . 0 C R T This is called as the delay equation
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Signal Waveform RC delay is calculated based on the risetime of the signal
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Constant Dimension Scaling • Transistors and Interconnections scaled by same factor • Lithography, pattern etching and material deposition remains the same • RC delay for global interconnections increases Constant Delay Scaling • Transistor and global interconnections scaled by different factors • Reduced RC delay/length cancels the increased chip size • Requires multiple levels of wires Scaling Vs RC Delay
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+ - << = - - RC t e e RC t t RC erfc t V RC t RC t out / 4641 . 9 / 5359 . 2 366 . 0 366 . 1 1 4 ) ( Distributed RC Line Distributed RC Lines
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How do you construct a Distributed RC Line ? Error decreases as number of sections increases
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lec5_interconnect_resistance_RC_Delay - Interconnect...

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