lec3_device_interconnect_scaling

Lec3_device_intercon - Device and Interconnect Scaling Ref Circuits Interconnections and Packaging of VLSI H B Bakoglu Addison Wessley(Out of Print

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Device and Interconnect Scaling Device and Interconnect Scaling Ref: Circuits, Interconnections and Packaging of VLSI, H. B. Bakoglu, Addison Wessley (Out of Print) Class Notes
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Device and Interconnect Scaling Intel’s IA-64 Itanium Microprocessor Have you ever wondered the following: How does a microprocessor run faster in each new product generation ? For example, in 1991, Intel 386 speed was 16MHz, in 1993, Intel 486 speed was 66MHz, in 1996, Pentium I speed was 300MHz, in 1999, Athalon speed was 900MHz and now Itanium runs faster than 1GHz.
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Device and Interconnect Scaling CMOS Technology Scaling CMOS Technology Scaling GATE SOURCE BODY DRAIN Xj Tox D GATE SOURCE DRAIN Leff BODY Dimensions scale down by 30% Doubles transistor density Oxide thickness scales down Faster transistor, higher performance Lower active power Technology has scaled well, will it in the future? Technology has scaled well, will it in the future? Courtesy: S. Borkar, Intel
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Device and Interconnect Scaling Moore’s Law Empirical law proposed by Gordon Moore in 1965. He made the observation that the components/chip doubles every 18 months Can be attributed to three major factors: Lithography (50% contribution) Increase in chip size (25% contribution) Innovation (25% contribution)
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Device and Interconnect Scaling What is Lithography ? Lithography determines the smallest feature size that can be fabricated on Silicon. The feature size has reduced by a factor of 2X in the last 5 years and continues to decrease Year 1997 1999 2001 2003 2006 2009 2012 Feature Size 250 nm 180 nm 150 nm 130 nm 100 nm 70 nm 50 nm Feature Size < Wavelength (Feature Size = Wavelength/2) Lithography is fast becoming a problem due to the small feature sizes 1000nm 100nm 10nm 1nm Deep UV Ex UV Xray Prox. E Beam 435 & 405
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Device and Interconnect Scaling Xj Tox D GATE SOURCE DRAIN Leff BODY Basic Operation of MOSFET
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This note was uploaded on 04/28/2008 for the course ECE 4460 taught by Professor Swaminathan during the Spring '08 term at Georgia Institute of Technology.

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Lec3_device_intercon - Device and Interconnect Scaling Ref Circuits Interconnections and Packaging of VLSI H B Bakoglu Addison Wessley(Out of Print

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