ECEN248 Lab 8

ECEN248 Lab 8 - Lab 8: The Priority Encoder Derek W....

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
Lab 8: The Priority Encoder Derek W. Johnson ECEN 248-506 Aaron Hill April 04, 2008
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Objectives This lab combines the student’s knowledge of shift registers and counters to construct a priority encoder. The student will become more familiar with the use of the internal clock and the 7-segment displays. Design 1. Debounced Clock (SR Latch) This design calls for the construction of an 8-bit priority encoder. In other words, an encoder that finds the most significant bit that is a one. Two shift registers and a counter were used to perform most of the work in the circuit. The first four least significant bits were loaded “backwards” into the first shift register. The least significant was connected to the A input, and the most significant was connected to the D input. In this arrangement, the shifter will shift out the most significant bit, then the second most significant bit and so on. The output, QD, of the first register was connected to the SER input of the second register so that it would shift in each bit shifted out by the first register. The second register was originally loaded backwards with the four most significant bits of the input number. This ensured that the first bit shifted out of the
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 04/29/2008 for the course ECEN 248 taught by Professor Lu during the Spring '08 term at Texas A&M.

Page1 / 4

ECEN248 Lab 8 - Lab 8: The Priority Encoder Derek W....

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online