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ECEN248 Lab 7

# ECEN248 Lab 7 - Lab 7 4-bit Shift Multiplier Derek W...

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Lab 7: 4-bit Shift Multiplier Derek W. Johnson ECEN 248-506 Aaron Hill March 28, 2008

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Objectives This lab will introduce the student to the onboard clock generator and will teach the student how to manipulate the speed of the clock using counters. This lab will also reinforce the student’s knowledge of shift registers and D Flip-Flops. The registers and flip-flops will be used to construct a multiplying circuit. Design 1. Clock Divider Circuit This design takes the internal clock of the Altera chip and slows the frequency down. A slower clock allows the user to see what his circuit is doing. The internal clock defaults to 25.175 MHz, and the design calls for a frequency of 1 Hz. Counters can be used to slow down the clock. Since each bit cuts the frequency in half, solve the following equation to find how many divisions are necessary. 2 X = 25175000 X = 24.6 Thus, twenty-five divisions are necessary to slow the clock frequency to below 1 Hz. Each counter has sixteen output bits, so two counters were used. The ninth output bit of the second counter was used as the clock output. In order for the counters to count up continuously, SETN and CLRN were connected to VCC, and DNUP and STCT were connected to ground. Because the counter only counts rising clock edges, an inverter was placed between the sixteenth bit of counter one and the clock pin of counter two. This ensured that the counter would stay in sync with the original clock. 2. 4-bit Shift Multiplier This design uses the new clock from design one, in combination with two shift registers and a ripple-carry adder, to create a multiplier. The circuit takes two 4-bit binary numbers, multiplies them together, and outputs the result to the seven-digit displays. The
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ECEN248 Lab 7 - Lab 7 4-bit Shift Multiplier Derek W...

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