ECEN248 Lab 6

ECEN248 Lab 6 - Lab 6: Shift Adders Derek W. Johnson ECEN...

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Lab 6: Shift Adders Derek W. Johnson ECEN 248-506 Aaron Hill March 7, 2008
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Objectives This lab will introduce the student to shift registers. Registers will be combined with a debounced clock signal and a single-bit full adder to form a shift adder. This lab will reinforce the student’s understanding of the “8count” chip and will introduce a use for a D flip-flop. Design 1. The Shift Adder In order to design a 4-bit adder using one full adder, some kind of memory must be used. The shift registers act as memory. Three registers are needed: two to remember each of the 4-bit numbers to be added and one to remember the result of the addition. In order to load a number into the register, the ST input had to be low and the LD input had to be high. If the ST input was high, then the register would shift as usual. For this reason, the LD input was connected to VCC. The SER input is the value that is shifted into the register on each falling clock signal, when ST is high. The SER was connected to ground to keep it from adding to the value of the number in the register. The CLRN pin of each register was connected to a global clear input (which was ANDed with itself for compiling purposes). For the CLK input, a SR latch was used to create a debounced
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This note was uploaded on 04/29/2008 for the course ECEN 248 taught by Professor Lu during the Spring '08 term at Texas A&M.

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ECEN248 Lab 6 - Lab 6: Shift Adders Derek W. Johnson ECEN...

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