ECEN248 Lab 3

ECEN248 Lab 3 - Lab 3 Adders Derek W Johnson ECEN 248-506...

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Lab 3: Adders Derek W. Johnson ECEN 248-506 Aaron Hill February 15, 2008
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This lab aims to increase the student’s understanding of ripple carry adders, and teach the student how to design multiple bit adders by combining single bit adders. This lab will also show the student how to implement adders with the fewest gates possible. Design 1. Half Adder The first step in designing a half adder is to write out the truth table. Table 1: Half Adder Truth Table A B C out S 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 The truth table shows that C out is an AND gate, and S is an XOR gate, both with A and B as inputs. The half adder does not take a carry input. The two gates can be placed side by side and can share the A and B inputs. See Figure 1. 2. Full Adder The only difference between a full adder and a half adder is that the full adder takes a carry input. Since it takes three inputs, the truth table is more complicated, and K-maps will be required to help interpret the logic. Table 2: Full Adder Truth Table
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This note was uploaded on 04/29/2008 for the course ECEN 248 taught by Professor Lu during the Spring '08 term at Texas A&M.

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ECEN248 Lab 3 - Lab 3 Adders Derek W Johnson ECEN 248-506...

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