{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

Package_Wiring_and_Terminals_Tummala

Package_Wiring_and_Terminals_Tummala - 2 PACKAGE WIRING AND...

Info iconThis preview shows pages 1–16. Sign up to view the full content.

View Full Document Right Arrow Icon
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Background image of page 2
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Background image of page 4
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Background image of page 6
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Background image of page 8
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Background image of page 10
Background image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Background image of page 12
Background image of page 13

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Background image of page 14
Background image of page 15

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Background image of page 16
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 2 PACKAGE WIRING AND TERMINALS KENNETH ROSE—Rensselaer TSUNEYO CHIBA—Hitachi WILLIAM R. HELLER—IBM (Deceased) WADIE F. MIKHAIL—IBM (Retired) 2.1 INTRODUCTION Digital circuits on semiconductor chips are the heart of the over— whelming majority of modern technology—based systems. Chips usually are housed in packages or carriers which are attached to a “planar” or printed—circuit board (PCB). However, there is a growing trend to attach bare chips directly to the PCB when size is critical. The circuits on these chips must be connected to their on—chip and off—chip circuits. Chips must be connected to each other through the carrier by terminals and ”wires” on these carriers. In turn, the carrier packages need to connect to yet higher levels with their own terminals and wires, creating a packaging hierarchy. Wireability is the ability to wire a packaging hierarchy successfully to meet digital system interconnection requirements under physical-design I—130 PACKAGE WIRING AND TERMINALS constraints. Interconnection requirements and physical-design constraints jointly define the density of terminals and wiring at all levels of the packaging hierarchy. This introduction reviews the development of the packaging hierarchy from the perspective of digital computer develop— ment, the changing requirements for physical design tools, and the need for a wiring model. Because the topic of package wiring and terminals is complex and its theoretical framework is still being formed, a detailed guide to the reader may be helpful. Section 2.2.1 introduces the basic model for understanding wireability—the amount of wire needed (wiring demand) must be less than the amount of wire available (Wiring capacity). The ratio of wiring demand to wiring capacity is the wiring efiiciency. Better wiring programs ’can improve this efficiency but it will remain around 0.5. It is helpful to scale wire lengths in terms of gate and module dimensions. This scaling is closely related to the concept of connectivity which has been used to estimate the wireability of printed wiring boards. . Wiring demand is proportional to the number and average length of pin—to-pin interconnections. (Note that a net connecting several pins 0r terminals will contain more than one interconnection. There are funda— mental, geometry-independent relationships between the number of pins, nets, and interconnections which are described in Section 2.2.5.) Section 2.2.1 provides some simple estimates of wiring demand and relates these estimates to connectivity estimates. Section 2.2.2 shows how a ,bfiitfiL. approximation of average interconnection lengths is given by Rentfs Rule, an empirical relationship between the number of gates in a motillilmeMa—nd~ the number of module input/output terminals. Donath derived an estimate of average interconnection length from Rent’s Rule by a hierarchical decomposition of logic designs. " Section 2.2.3 considers limitations to Rent’s Rule and the effect of fluctuations in the number of gates and terminals for a‘ module. This discussion continues in Section 2.2.4 which considers models for the distribution of interconnection lengths. Knowledge of the wiring distribu— tion allows one to account for fluctuations in wiring demand in addition to estimating average interconnection length. Section 2.2.6 shows how this allows development of a probabilistic model for wiring success. Section 2.3.1 compares model predictions to experimental results for chip wiring. The results can be expressed succinctly by plotting the logarithm of available wiring tracks versus the logarithm of wireable gates for a chip (Fig. 2—18). 90% probability of successful wiring is represented by a straight line on this plot. This line guides the chip or package designer by indicating the boundary between conditions for wiring success and failure. Sections 2.3.2 through 2.3.6 indicate the influence of a variety of practical considerations on chip wireability. In Section 2.4 this theory is extended to higher-level packages. 2.1 INTRODUCTION l—131 Section 2.4.1 compares the estimates of researchers on wiring demand and wiring distributions for printed wiring boards. Explicit mention is made of the effects of through-hole or via constraints on wireability. Difficulties peculiar to higher-level package wireability are considered in Section 2.4.2. Section 2.4.3 reviews detailed experiments on the constraints which via availability and wiring—track accessibility impose on package wireability. Overflow, the fraction of wires which could not be wired by an automatic wiring program, are used as a measure of wiring difficulty. Section 2.2.4 presents a quantitative model for predicting overflows. The use of wireability analysis in higher level packaging is illustrated in Section 2.4.5 by applying it to Ball-Grid Arrays (BGAs) and Quad Flat Packs (QFPS). . Conclusions and challenges for future work are summarized in Sec- tion 2.5. A case is made for the overall value of wireability analysis in Section 2.5.1. The influences of preplacement and prewiring on wireability are discussed in Section 2.5.2, mixed-signal wiring in Section 2.5.3, and the challenges for computer—aided design tools in Section 2.5.4. 2.1.1 The Packaging Hierarchy Wireability issues became an important problem early in the develop— ment of mainframe computer systems because of the need for reliable, high—Speed interconnections between thousands of circuits by thousands of wires. This led naturally to a “top—down” design methodology, which included a nested set of packaging levels constituting a physical hierarchy. In this way, one could simplify the logical design and the interconnection of circuits by concentrating attention on one level at a time. More impor— tantly, one was able to make the manufacturing process and its tools modular. Finally, one could aim at testing subunits before final assembly, thereby easing diagnostic work and assuring high quality levels in the system product. This allowed designers to address what has become called the “known good die” problem for multichip modules. However, along with the advantages of hierararchy come problems of structure, materials, and the processing of package terminals on each level of the package hierarchy. These will be discussed in subsequent chapters. The number of terminals at each level increases with circuit count. This is discussed in Section 2.2.2. There are both geometrical and electrical constraints on the accessibility to wires and the location of terminals. One of these constraints comes from the minimal dimensions and processing tolerance limits on spacing of the terminals. Another constraint is the need for “redistribution wires” or “space transformers” from terminals on one level of the packaging hierarchy to terminals whose spacing is determined by corresponding limits on the next higher level. Figure 2-1 illustrates the role of this redistribution. Space must also be [—132 . PACKAGE WIRING AND TERMINALS . metallurgy and "' redistribution - layers ; Signal —‘ distribution and 1 signal reference layers distribution and module 1/0 layers “ we 3” . v a \ E g. “4" Figure 2-1. IBM Multilayer Ceramic. Construction detail of the multilayer ceramic used in the IBM Thermal Conduction Module. (From Ref. 1, © 1982 by IBM Corporation; reprinted with permission.) provided for the terminals required for engineering changes and repair near the signal terminals at the interconnection points of different levels. 2.1.2 Wiring Constraints and Dimensions A familiar picture to the owners and users of older computers was the apparent tangle of single “yellow” wires interconnecting circuits on the back panels (Fig. 2—2). This was possible for two reasons. First, the large circuit delays dwarfed the interconnection delays of even several feet of wire and put no premium on the use of printed wire or cables for speed and shielding. Second, very early in digital—system history the number of wires became large enough to make the automation of wiring in manufacturing advantageous. Special machines (e.g., those developed by the Gardner—Denver Company) were devised to secure and route these INTRODUCTION I—133 Figure 2-2. Back Panel of IBM Standard Module System (SMS). Gold tabs on cards mated to cantilevered pins on the back panel. wires from pin to pin on the back panels. Automated handling by these machines required instructions on a sequence of punched cards. Programs to make, check, and change these cards became the first design—automation tasks, along with the recording of originals and changes in the inventory of parts required for assembly. Very rapidly in the history of system development, however, the need for delay and cost reduction forced technologists to develop printed wire for packages and the techniques of fine—metal—wire deposition for the later development of chips. It became obvious that manufacturing simplicity required an arrangement with the wiring on successive layers of the circuit board directed predominantly in mutually perpendicular directions. Multiple—layer wiring also made necessary the development of between-plane connectors, or “vias,” between wires on different planes. The terminals of the package to be mounted on this board had to be located on a regular grid of such via positions, with terminals alternating with needed vias, according to demand. Figure 2—3 illustrates this. This style of printed—circuit—board wiring has now been translated on to the integrated circuit chips which use multilayer metallization to meet wiring demands. In later developments, first on-chip and more recently at higher package levels, it has become possible to ”program” the location of vias interconnecting adjacent wiring levels at “off—grid” positions. Even at “on— giid” positions, vias may be segmented to individual pairs of wiring planes. I—134 _ PACKAGE WIRING AND TERMINALS E. H {1‘ 'd a t: L}. (c) l V I (d) Figure 2-3. Wiring Planes in IBM Logic Cards. (a) Standard module system card- 1959, IBM #1401 computer; 03) solid logic technology modules cards and boards—1964, IBM #360-30 computer; (c) monolithic systems technology modules cards and boards— 1969, IBM#370—l45 computer; (d) large—scale integration cards and boards—4979, IBM#4341 processor. (From Ref. 3, © 1981 by IBM Corporation; reprinted with per- mission.) Much of the work reported here was done in connection with large, high-performance systems and, hence, relatively large wiring boards. One may ask whether larger planar boards offer the best engineering solution to wiring capacity when lowering costs while designing systems with less . than technology—limited speed. In this situation, it may be advantageous to use fewer wiring planes to hold the chip carriers and to stack the 2.1 resulting C , . . . . . be air cooled, it can give Circult-volume dens1ty at lower cost, superlor to an entirely planar arrangement. Conventional integrated-circuit packag— ing for systems, as illustrated in Figure 2-4, is representative of present workstations and personal computers. The wireability of the individual cards is curtailed if their input—output terminals extend only along the edge Where they plug into the board. Unpublished studies by W.E. Donath show that the local “escape” problem near these I/Os results in about a 20% reduction in overall wiring capacity per card. This may still be acce carrying modules. In the IBM RS/6000 workstations using the POWERTM technology, all processor components except main memory are mounted on a single, planar printed wiring board (PWB). The low—connection requirements of memory chips allow them to be mounted on cards at angles to this board. INTRODUCTION I—135 ards on their edges on a board. When this configuration can ptable if taken into account when populating the card with its chip- The demands of low—cost packaging have led to emphasis on the Figure 2-4. Conventional Integrated-Circuit Packaging. Waf cessing consists of dicing the integrated-circuit chips from the silicon wafer, bondlng the chip to a substrate, soldering the module onto a card, plugging several cards into a board, cabling the boards into a gate, and attaching the gates to the machine. (From Ref. 45, © 1982 by IBM; reprinted with permission.) l~136 PACKAGE WIRING AND TERMINALS surface mounting of components on packages [2]. With this technique, chips or chip carriers (with or without leads emanating from the the chip or carrier pads) are soldered directly onto metal pads on the substrate. Spatial fan-out from these pads on the same surface is made to Vias on the wiring grid below. Some wiring between components can also be done on the top surface. This is in contrast to the older scheme in which the chip is held on a carrier having pins which fit into an array of plated— through-holes (Vias) in the substrate. Knausenberger and Teneketges [2] have shown that if the via diameter dictated by the surface—mount pads is appreciably narrower than that of through holes, more wiring tracks are available on all wiring planes of a card package. This, in turn, means that more chips can be mounted and successfully wired on the package. A final aspect of importance in the interconnection distribution is the location of input and output terminals of the package on which the entities to be wired together are mounted. These may be located peripher- ally on the package or spread out over its area, with differing influence on the ease of wiring, as we shall see. Very similar concerns were being addressed by system designers in other electronic industries who were concerned with how large a circuit board was required to interconnect a set of integrated circuit (IC) chip packages [4]. On the whole, this has been a “bottoms-up” approach to packaging, where designers constructed systems by mounting prepackaged components on printed—circuit boards available from the printed—wiring— board industry [5]. This has been the approach used by the manufacturers of personal computers. Recently, CMOS (Complementary Metal-Oxide Semiconductors) has become the dominant IC technology because shrinking device dimen- sions and low power consumption have allowed millions of transistors to be placed on a single chip. Very Large Scale Integration (VLSI) has had several consequences for the packaging hierarchy, the most noticeable of which has been the convergence of mainframe and personal-computer packaging approaches for workstations. Because wireability is a consider— ation for the entire system, on—chip as well as off-chip interconnections need to be addressed. In VLSI systems, partitioning directly influences physical design. 2.1.3 Influence of Physical-Design Tools on Package Wiring The increasing number of circuits housed on digital packages has forced changes in the physical-design software. By “software” we mean primarily those application programs which place circuits on chips and chips on chip carriers, assigning input and output terminals and defining the interconnections among all these. There are two principal constraints that VLSI packages bring to the development of such programs. One of 1' i I 1 l l l . 2_1 INTRODUCTION [—137 these is the increase in customization required at all levels of the package hierarchy. The other is the increased emphasis on circuit performance which is imposed by the larger proportion of overall system delay (itself continually getting smaller) contributed by the wiring and connectors. Both of these constraints mean that placement, wiring assignment, and routing programs must handle trade—offs more sophisticated than the Simple reduction of wire length. Beyond the limits set by delay, they must relate in a smooth and timely fashion to the electrical constraints (wiring rules) and requirements of logic design (e. g., automatic or semiau- tomatic synthesis and partitioning). In relatively low—cost and small sys- tems, the emphasis on design simplicity dominates. In relatively fast and large systems, timing considerations dominate. New technologies (surface mounting, significantly three—dimensional circuit deposition [6], polyim- ide, and ceramic substrates) also have their impact on the design methodol- ogy and algorithms. 2.1.4 The Need for a Model of Wiring It is clear from the description in the last section’s that when the number of connections on a given package level reaches the thousands or tens of thousands, one has to deal with a set of extremely complex combinatorial problems. Powerful algorithms based on ingenious heuris— tics have been programmed to deal with these problems [7—12], which are of the difficult class characterized by “nonpolynomial solvability.” From the point of view of digital-systems design, it can be seen that this creates a set of planning and architectural challenges. Not only must the system designer develop a View “in the large” of the system subfunctions and their interconnection, he or she must also face important economic and scheduling questions involved in reconciling architectural, logical, and physical design. To resolve these questions the system designer needs to be able to predict the size and wiring capabilities of the physical packages on which the system logic is to be placed and interconnected. These predictions can only be probabilistic, inasmuch as the precise knowl— edge of system logic, let alone its partitioning, placement, and detailed interconnection, is necessarily lacking at the early stage when package choices are to be made. The problem is compounded in mainframe or supercomputer design, where hundreds of logic and memory “parts” must be designed, usually in parallel, in general after the chip and package images have been chosen. A part, in this sense, must be defined as a subproduct coming from a group with similar dimensions and connector patterns but having a unique design for a unique function. With a regular package image (Le, a pin arrangement with repeated sites) at the next higher level, one can manufacture several parts that are distinct in function but have a similar |—138 PACKAGE WIRING AND TERMINALS image interface to the next higher package level. Such parts constitute individual “part numbers.” Along with the possible repetitive use of part numbers, such an arrangement permits spatial rearrangement of the parts at a given level of the package hierarchy in order to shorten wires, relieve cooling problems, or satisfy other system constraints. In the next subsec- tion, we discuss the goals of a possible package wiring model. 2.1.5 Goals for Quantitative Prediction , Some general properties of the placement of circuits, the assignment of terminals, and the allocation of wires must be characterized in order to model the packaged part numbers making up the system. In turn, one wishes to predict the number of package wiring tracks and wiring planes required to accommodate the subpackages to be placed on the package surface. It should be recognized that there are two distinct uses for the predictive modeling tool. For a given system plan, one needs to allot sufficient package space from an available suite of chip and package types. In order to plan future systems, on the other hand, one wants to plan wiring space as well as terminal count and locations in chips and packages yet to be developed. In subsequent sections, a model is presented that is useful for projecting sufficient wiring space for chips to provide high confidence in automatic placement and wiring with few overflows [13]. A related model permits projection of the range of package wiring overflows expected, given information about the number and terminal count of subpackages to be placed on the package [14,15]. From such a wiring model, one can predict the number of tracks required to wire a given number of circuits with 90% confidence. Depend— ing on the number of connections per circuit, one can determine a band within which automatic wiring programs should be successful. Comparing this with experience in wir...
View Full Document

{[ snackBarMessage ]}