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Unformatted text preview: 1/8 EE 319K Fall 2008 First Mid-Term Dr. Ramesh Yerraballi Full Name : Duration : 75 minutes This is a closed book exam; No calculators are allowed; Write answers within the space provided after each of the questions. There are SEVEN questions on the test, read all of them first so you may properly allocate your time to answer them. 1. [ 20 pts ] Answer the following a. Consider the following 8-bit number: %10011011 i. What decimal value does it represent if it is an 8-bit signed integer? You could either use the basis method or do the 2’s complement method Basis: -128 + 16 + 8 + 2 + 1 = -101 2’s Complement: 2’s complement of the number is 01100101, which is 101 and since it is a negative number = -101 ii. What decimal value does it represent if it is an 8-bit unsigned integer? Basis: 128 + 16 + 8 + 2 + 1 = 155 b. What will be the value of the carry bit C after executing the following? ldaa #120 adda #200 Addition of two unsigned numbers result in the C bit being set when an overflow/underflow occurs. 120 + 200 = 320; The largest unsigned number we can represent in 8-bits is 255. So there is an overflow and the C bit is set to 1. c. What will be the value of the overflow bit V after executing the following? ldaa #-80 adda #-120 Addition of two signed numbers result in the V bit being set when an overflow/underflow occurs. -80 + -120 = -200; The smallest signed number we can represent in 8-bits is –128. So there is an underflow and the V bit is set to 1. d. What will be the value of the A register after executing the following? ldaa #$05 ; A : $05 (%00000101) lsla ; A : (left shift) $0A (%00001010) oraa #$A0 ; A : $0A OR $A0 = $AA (%10101010) asra ; A : (Shift right) %11010101 ($D5) 2/8 2. [ 10 pts ] Identify the addressing mode used in each of the following instructions: Instruction Addressing Mode subd 2,x IDX – Indexed Clra INH - Inherent ldaa #$36 IMM - Immediate ldd $3800 EXT - Extended bra loop PC-REL – PC Relative 3. [ 10 pts ] Complete the following branch condition checks: Unsigned Signed Branch Check Branch Check blo(bcs) C = 1 blt (N^V) = 1 bls C + Z = 1 ble (N^V)+Z = 1 bhi C + Z = 0 bgt (N^V)+Z = 0 bhs (bcc) C = 0 bge (N^V) = 0 Hint: The rest of the checks can be derived from the ones provided bhs is the complement (opposite) of blo therefore the condition checked is the opposite. bls is “less than or same” so we have to add Z being 1 to blo (just less). bhi (higher) is the complement of bls (less than or same). bge (greater or equal) is complement of blt (less than). ble checks for zero in addition to blt . bgt is the complement of ble . 4. [ 10 pts ] Assume a bsr process instruction is located at address $5050 and the address of the subroutine process is $5082....
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This note was uploaded on 02/19/2009 for the course EE 319K taught by Professor Bard during the Spring '08 term at University of Texas.
- Spring '08