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CSE 240 Autumn 2005
DUE: Mon. 10 October 2005
Intro. to Computer Architecture
Homework 4
Write your answers on these pages. Additional pages may be attached (with staple) if necessary. Please ensure that
your answers are legible. Please show your work. Due at the
beginning of class
. Total points: 80.
1. [6 Points]
Instruction Encoding.
Suppose a machine encodes instructions in 32 bits according to the following
format. Also, suppose the encoding must accommodate 164 opcodes and 50 registers.
OPCODE
SR
DR
IMM
(a) What is the minimum number of bits required to represent the OPCODE ﬁeld?
Answer
: Seven bits can represent 128 values (2
7
=
128), so (in this case) seven isn’t enough. Eight bits
can represent 256 values (2
8
=
256), so we need eight bits to represent 164 values. Unfortunately, we are
not making efﬁcient use of these bits. If possible, the ISA designer might want to ﬁnd a way to get the
number of opcodes down to 128, so that opcode may be represented in one fewer bits.
(b) What is the minimum number of bits required to represent each of the register ﬁelds (
e.g.
, DR)?
Answer
: First, it is important to observe that both register ﬁelds (
i.e.
, SR, and DR) can name all registers,
so they will all be the same size. Five bits isn’t enough, because 2
5
=
32
<
50. Six bits is just enough,
because 2
6
=
64
>
50. Heck, why not give this machine 64 registers? It won’t increase the encoding space.
(c) What is the greatest number of bits that are left for the IMM ﬁeld? If the IMM ﬁeld encodes a 2’s comple
ment integer, what range of values can be represented with these bits?
Answer
: We know the whole instruction is 32 bits and the opcode consumes eight bits and each register
ﬁeld consumes six bits (for a total of 6
×
2
=
12 bits). We are then left with 32

8

12
=
12 bits for the
immediate ﬁeld. In 12 bits we can represent 2
12
=
4096 different values, speciﬁcally the range of integers
from

2
11
=

2048 to 2
11

1
=
2047.
2. [8 Points]
Instruction Processing.
The PC, IR, MAR, MDR, and RF (register ﬁle) are structures written (and
read) in various phases of the instruction processing cycle, depending on the instruction being executed. In
each table cell, below, enter the instructions that result in
writes
to the corresponding structure (row) during the
corresponding phase (column) of the instruction processing cycle. For example, place LDR in the PC row of the
FETCH column if LDR causes the PC to be written during the FETCH phase. To make this simpler, let’s only
consider the following instructions: ADD, LDR, LEA, ST, and TRAP. The textbook doesn’t directly answer this
question (
i.e.
, you can’t just “look it up”), so your answers will need to be based on your understanding of what
should happen in each execution phase.
Answer
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 Fall '08
 LEWIS
 Computer Architecture

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