Final_Solution_W06 - ECE124d/256c Final Examination...

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Unformatted text preview: ECE124d/256c Final Examination March 20, 2006 ECE124d/256c Final Exam March 20, 2006 Problem 1. (24pts.) % SS Problem 2. (20pts.) 30, \0 Problem 3. (30pts.) Zg ,\ 0 Final score (74pts) Name: g L \( Name’ - pa 09. 1 ECE124d/256c Final Examination March 20, 2006 r (24 pts) Pmb 1. 0n the first day of your consulting job, the marketing people at the firm (a fabless chip vendor) would like you to estimate the power dissipation of several possible memo- ry interfaces for their current flagship product. This chip needs 2 DDR interface channels of 80(64+16) active wires each, running at 250MHz switching rate. In all cases, the lines are ef- fectively terminated ( but do not have D. C. paths to ground). a. Case 1, the memory chips have a SpF load and are at the end of a 250pS long 60 ohm trans- mission line, and use an LVT T L (3.3 V full swing interface). F%”7 {WWW 1”“ c i ' ' i9»..r Sis/- ’ ~. 3—:ka 1’“ 33V (0032’ T62; 60n— & CV .. L “Y2 m a swim» 5*: aw ‘ v- ECE124d/256c Final Examination ' March 20, 2006 6. Case 3, (server version) uses several banks of chips with a total load of 25pF, and are located up to 1118 away on the 50 ohm TM line, but use a ‘new technology’ GTL interface: 600mV % swing out of 1.8V supply (this means that the output level goes from 700mV to 1.3V-- and the Name! pa 0?. ’1 ECE124d/256c Final Examination March 20, 2006 (20 pts) Prob12.‘1n a large ASIC design, the "following circuit was used to generate a gray-code counuwv state b 2b Ibo Bit fn s0 000 ha = Next(51®b2) SI bl = Next(b052+b130+b132) s2 011 b2 2 Next(Next(b1)) s3 010 S4 110 (Next() implies a flip-flop delay) s5 111 s6 101 s7 100 (aka): a. 1n the original design (using non-Overlapping clocking), this counter functioned correctly, however, in the new edge-triggered version, the counter fails in all speed versions. Since the de- 10 sign is so simple, everyone is perplexed -- but you see a possible problem. Describe why this simple design might be failing and propose a simple fix. Jade" 2"" (H9253- V US he; r~ WW 3’6 0L” rm r» w o U—asi‘mf Cfioa.{£-.1~"~A\E* goxwe" “f “\n’k’é N M a .2 editn .. b. In the design, this counter is used to drive a large decoder array -- so, efiectively, each of the counter bits is driving a fanout tree with nearly 1000 10fF gate loads. Why was this code cho- sen instead of a conventional binary counter, given that the order of the count did not matter in the design? Hint: at the 500MHz operating frequency, determine the power dissipation of this circuit driving its loads, versus a binary counter design. 1 , <3, v Q/ooéi '5‘: [OOO "t.- L . "- 41‘"; 0mm” Ier‘a \o ECE124d/256c Final Examination March 20, 2006 (30 pts.) Prob. 3. You are called in to help double the clock Speed of an existing 200MHz design. The chip is 5.5mm square and is to be area bonded in the new technology, which boasts tech- nology having less than half of the inertial gate delay of the original design. You are to design a clock grid to drive the entire design of 20, 000 14.5fFflip-flops synchronously. You need to have a 200pS rise time at the flip-flap inputs an can stand no more than 5 00pS jitter+skew to meet the timing margin. a. The grid covers the entire chip and uses 15% of the metal in layer 4. Layer 3 is 0.75am away and is a ground plane, the effective dielectric constant is 2.5 in this technology. A massive clock driver is plann ed for the center of the die, driving the grid which directly drives the flip-flops. Despite your misgivings about this approach, estimate the capacitance of the grid, the current to drive it with a 200pS rise time. Design a buflering scheme to drive the grid from a 5 00uA clock source given full swing clocking, 1.8V Vdd, 10k ohms/sq. saturated n-Channel equivalent resistance, 19kohms/sq. saturated p-channel resistance, 3.2fF/um2 gate capacitance and a 0.1 Sum minimum channel length. Find the total power dissipation of the clocking scheme. (Ne- glect the resistance ofthe clock grid). («90 “=1 <5 Kb 54 1. 5‘” 5/0... . - 6 (S MW‘ Y (“59x 5? f t; fxflk ,7 f- _ ,E. . e’ f 1" ,. I ‘ ' ,3: ea .2, a: C a - I r m a , .1- ‘ __ m g. Q Slma 2»? a M [’S3’Wm 6 :(Céflw‘ 2M, ‘61) Li M '9“) w» v «/ mayo.“ \\ "zed/W . Jar“ p, _ ‘ ' C/ 7, .1 1-‘- <5 rd? go rear? \\ WP U010 ’6; H9 Y? .\ it ‘ ... 43° = H" {MM/o 1-3 B % v" ‘ “N‘ Cr f O z") 2.;— A 6: F (wt. , )c- “i ‘ V 1 ’ WQ(J\’-iv“k_ ....--’ Q), \ A'bxei " “5 S C ’- ... t ’1,- ‘ q" H . mm M w 1 NJ- ; a ' ' / i ...... Mimi? ,,, ,. 7 3" O if 7*“ LO E p z’ i r I M\/ fgfonK-‘rifi #6 N \qc, 3k £L\&I,Q ECE124d/256C Final Examination March 20, 2006 b. This plan bothers you as it seems to have the potential for a substantial amount of power cou- pled noise in the chip. How much on-chip decoupling capacitance is necessary to keep the clock buffer from pulling the supply down by more than 90mV during the clock transitions? Pace. 6 Name} ...
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