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quiz3_09_soln

# quiz3_09_soln - ECE124d/ECE256C Name'4 2 g 1 3 ’T Rw 2...

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Unformatted text preview: ECE124d/ECE256C ' Name: '4 2%; g 1 3:: ’T ' , Rw 2 425mm ' “uh ,5; +1 " 1:05:13? 5, Cw = 230fF/mm ” I? ..—~ EINV = 16% £ 4 CLINV = 10fF*h C Cc :- 3: 5" Consider the net extracted from a chip design above. The chip has already been routed, but ﬁnal buffer insertion (adding buffers to speedup the wires) has not been done. All of the gate drive capabilities have been scaled in terms of a minimum inverter whose RC characteristics are shown in the picture. (h=16 here in the gate indicates that its drive capability is 16x that of a minimum inverter, as well as the parasitic input capacitance, the output capacitance is assumed to be zero) a. Estimate the delay time for the net from the driver (D) to points A, B, C. T14: MK- 519+ ZIZ'.9ZS+ tDL-.71.n = Laus’ TV Two-133a“ aka-.223 + isms» = 1-12.? "(75, =— 2}. +5a.x.3n’+ 199' .25?+ 9,1300: 1.5%? b. The delay found in part a was too long -- additional buffering of the line is required. Assuming a single inverter is added at point A to drive both lines, ﬁnd the inverter size h to minimize the delay to point B. What is the delay to B for this case? To 2 7TH“ +7200 Elﬁz‘f‘w'” k + 1594-1237,: 2M,+ 14.214 7;: ”91.36 +- Hzp ‘0 Te“)- H 2. _. 1.2.15. an“ =0 h ' bk ’ ' be 1. lLlc'.3‘5\$ .121, ‘43-'21 =3 1“: tel-2. '— ‘C3 2 And-.413 = 1.0%: c. What is the change in power to drive this line given your additional buffer? Why is the power noise induced in the supplies worse than this? nag—paw» 407.. exam pm! :21- MP we {F =. 410 ~ ., Tat-=1 ref aka-«a, 9‘10 1:: -_—_ 22.?2 4MMC-3? 7:.) PMT—ui’Q‘Z. ) “ (2X Safes-M boat. a) ,aWM—“D’WW '— _ 10on M 6725 Nan-4 5m 74%.... ...
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