Lecture_12_BEOL

Lecture_12_BEOL - Lecture 12 Metallization / Back-end...

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Metallization / Back-end technology (BEOL) Lecture 12
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IH2655 Spring 2009 Mikael Östling KTH BEOL in VLSI: Interconnects and dielectrics Multi-level metallizations: (VLSI p415) 6-7 wiring levels in 0.18/0.13 μ m CMOS For yr 2010, up to 9 wiring levels for 0.07 μ m Cu metallization with etched off dielectrics, IBM 1997
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IH2655 Spring 2009 Mikael Östling KTH • More metal interconnect levels increases circuit functionality and speed. • Interconnects are separated into local interconnects (polysilicon, silicides, TiN) and global interconnects (usually Al). • Backend processing is becoming more important. • Larger fraction of total structure and processing. • Starting to dominate total speed of circuit.
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IH2655 Spring 2009 Mikael Östling KTH ¾ Circuit feature size continuously decreases, and current density increases ¾ The number and length of internal connections increase rapidly ¾ The number of metal levels and the metal aspect ratio (AR) increase From ITRS2006
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IH2655 Spring 2009 Mikael Östling KTH Historical evolution of BEOL 1960s: ( Plummer p 687 ) 1970s: ( Plummer p 695 )
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IH2655 Spring 2009 Mikael Östling KTH 1980’s: (Plummer p 703) 1990’s : (Plummer p. 707)
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IH2655 Spring 2009 Mikael Östling KTH • Next development was use of other materials with lower resistivity as local interconnects, like TiN and silicides. • Silicides used to 1. strap polysilicon 2. strap junctions 3. as a local interconnect.
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IH2655 Spring 2009 Mikael Östling KTH • Two backend structures. Left: three metal levels and encapsulated BPSG for the first level dielectric; SOG (encapsulated top and bottom with PECVD oxide) and CMP in the intermetal dielectrics. The multilayer metal layers and W plugs are also clearly seen. Right:five metal levels, HDP oxide (with PECVD oxide on top) and CMP in the intermetal dielectrics.
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IH2655 Spring 2009 Mikael Östling KTH Interconnect delay (Plummer p 685) Line resistance, interconnect coupling and substrate coupling all contribute to an RC delay where A = chip area and F min is minimum feature size Current 0.18 μ m CMOS: 30-40% of delay due to interconnects! 2 min ) ( 89 . 0 F A ox L ρ ε τ=
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IH2655 Spring 2009 Mikael Östling KTH Methods to reduce interconnect delay: 1) Low-resistance metal ( Cu ) 2) low-k dielectrics
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IH2655 Spring 2009 Mikael Östling KTH Interconnect delay cont’ Շ g is gate delay in CMOS ring oscillator (Plummer p683) Interconnect RC crisis partly postponed by increased dimensions and spacing of the highest level of interconnects (“fat wiring”)
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IH2655 Spring 2009 Mikael Östling KTH (Sze p 376) Contact resistivity Metal-Si contact must be ohmic, i.e. a tunneling contact Low contact resistance RC RC = ρ c/Ac where ρ c is contact resistivity [ Ω cm2] and Ac contact area High doping in Si required (>6x1019 cm-3) Thermal stability: Avoid degradation during subsequent processing: Forming gas anneal (FGA) or post-metal anneal (“alloying”) Barrier layers, e.g. TiN, TiW or silicides
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IH2655 Spring 2009 Mikael Östling KTH BEOL definitions Local interconnects: 1 st level of metallization On device level In the past: Al Now: Heavily doped polysilicon and/or silicides Must withstand high temperatures ~800 ° C
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Lecture_12_BEOL - Lecture 12 Metallization / Back-end...

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