Lecture_13_Process_Integration

Lecture_13_Process_Integration - Lecture 13 Process...

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Process Integration Lecture 13
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IH2655 Spring 2009 Mikael Östling KTH Lithography Laser, E-Beam, … Thin Film deposition CVD – LPCVD, PECVD, … PVD – Sputtering (DC, RF, …), Evaporation (Resistance, E-Beam), … Epitaxy Spin-coating inkjet printing Etching Wet etching Dry etching Doping Ion implantation Diffusion Surface engineering Thermal oxidation Metal silicide SALICIDE Pattern Thin Film
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IH2655 Spring 2009 Mikael Östling KTH ¾ MOS Isolation ¾ Composite Gate and Self-Alignment ¾ Advanced CMOS Integration
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IH2655 Spring 2009 Mikael Östling KTH MOS-Basic Isolation in ICs MOS transistors are self-isolation. Compared with bipolar devices, MOSFETs may have higher density, but they will suffer from the parasitic effects from the adjacent devices. 9 High thersold voltage at the field region V TF is preferred. V TF must be 3-4 V higher than the supply voltage to ensure that the current from parasitic MOSFET is less than 1 pA. 9 V TF decreases with decreasing device distance or increasing temperature T . When T increases from 25 o C to 125 o C, V TF will decrease by 2 V. Methods to Increase Field Threshold Voltage V TF ¾ Thicken field oxide to be 7~10 times thicker than gate oxide ¾ Increase the doping concentration under field oxide (Channel- stop implantation) ox C MS A qN s MS FB T V V ) 2 ( 2 2 φ ε + + =
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IH2655 Spring 2009 Mikael Östling KTH 1. LOCOS Isolation Technology (40nm) (80nm) 50 keV 1 × 10 13 cm -2
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IH2655 Spring 2009 Mikael Östling KTH Problems in LOCOS Technology 1) Bird’s Beak Effect —bad to integration improvement 2) Rough Surface —bad to Lithography and Thin Film Deposition
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IH2655 Spring 2009 Mikael Östling KTH Improved LOCOS — PBL (Poly-Buffered LOCOS) Deposit a layer of polysilicon before LPCVD Si 3 N 4 . Polysilicon consumes the oxygen diffused laterally during field oxidation. The bird’s beak can reduce to 0.1-0.2 μ m.
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IH2655 Spring 2009 Mikael Östling KTH PBL Helpful to integration improvement
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IH2655 Spring 2009 Mikael Östling KTH 2.STI (Shallow Trench Isolation) LOCOS, PBL applicable for technology node 0.35-0.5 μ m. For technology node <0.35 μ m, STI must be used. 1) Wafer Cleaning 2) Substrate Oxidation (20 nm)
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IH2655 Spring 2009 Mikael Östling KTH 3) LPCVD Si 3 N 4 (100 nm) 4) Isolation Lithography 5) Shallow Trench Etching (0.5 μ m)
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IH2655 Spring 2009 Mikael Östling KTH 6) Thermal Growth of Oxide Stop (20 nm) 7) Channel Stop Implantation 8) Trench Filling by CVD Oxide
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IH2655 Spring 2009 Mikael Östling KTH 9) Etching-back Planarization 10) Si 3 N 4 Etching
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IH2655 Spring 2009 Mikael Östling KTH 11) Re-Etching-back Planarization 12) Densification Annealing of CVD Oxide
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This note was uploaded on 03/09/2009 for the course EE 300 taught by Professor Y during the Spring '09 term at CUNY City.

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Lecture_13_Process_Integration - Lecture 13 Process...

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