l9_handouts_4up - Announcements ECE 3140/CS 3420 Computer...

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ECE 3140/CS 3420
Computer Organization
Spring 2009
Sequential
Digital Logic
ECE3140/CS3420
Announcements
• Project 2
– Due Tue, Feb 21 at 10:00pm
ECE3140/CS3420
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Hennessy and Patterson
• Read Chapter 1
– 1.1-1.9
• ead Chapter 2 Read Chapter 2
– 2.1 through 2.14
– MIPS Calling Convention Document (website)
– Notes on Programming in C (website)
• Read Chapter 3
– 3.1 through 3.2
.3 through 3.5 (for Tuesday)
ECE3140/CS3420
3.3 through 3.5 (for Tuesday)
• Read Appendices C
– B.1-B.6, B.10, C.1-C.10
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Today’s Topic
• Digital Logic
– Sequential
• Verilog Hardware Modeling
– How to implement digital logic using a HDL
– Verilog syntax/details to be covered in section
ECE3140/CS3420
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Sequential Circuits
• The output of a sequential circuit depends on
current inputs and past inputs
– I.e., circuit “remembers” past events p
• Idea:
– Introduce devices that can hold state
• Called state-holding elements (e.g., flip-flops)
– Next state depends on previous state (stored in stat-
holding elements) and circuit inputs
utputs depend on previous state and circuit inputs
ECE3140/CS3420
Outputs depend on previous state and circuit inputs
– Next state and outputs calculated using combinational
circuits
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State Machine Structure
Combinational
Logic
inputs outputs
next
state
current
state
ECE3140/CS3420
State
Memory
clock
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D Flip-flops
• A flip-flop is a 1-bit memory
– Stores 1 bit of “state” information
– Changes state on each “tick of the clock”
• Positive edge-triggered flip-flops
D CLK Q QN
ECE3140/CS3420
0 ↑ 0 1
1 ↑ 1 0
x 0 last Q last QN
x 1 last Q last QN
x ↓ last Q last QN
D Q
QN
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D Flip-Flops
• Negative edge-triggered flip-flops
D CLK Q QN
0 ↓ 01
• Positive edge-triggered FF’s with enable
1 ↓ 1 0
x 0 last Q last QN
x 1 last Q last QN
x ↑ last Q last QN
D Q
QN
D EN CLK Q QN
0 1 ↑ 0 1
ECE3140/CS3420
D Q
QN
EN
1 1
↑
1 0
x 0 ↑ last Q last QN
x x 0 last Q last QN
x x 1 last Q last QN
x x ↓ last Q last QN
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Registers
• An n-bit register is a