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Unformatted text preview: ECE 315 Homework 6 Solution Spring 2009 1. (MOSFET subthreshold and saturation behavior) Consider a NMOSFET with a threshold voltage of V th =0.7V, threshold current I th =10 μ A and the substrate factor κ =0.8, (a) If the gate oxide thickness is 10nm, what is the depletion region width in silicon to obtain this substrate factor (hint: the dielectric constant of SiO 2 ε ox at 3.9 and Si ε si at 11.7)? (4 pts) C ox = ε ox ε /t ox = 3.45 × 107 F/cm 2 . κ =0.8= si ox ox C C C + , and we can find C si = C ox /4 = 8.63 × 108 F/cm 2 = ε si ε /W d . Hence, W d = 0.12 μ m. (b) Estimate I D at V GS =0.3V and V DS =0.0V. (4 pts) At V DS =0, I D is required to be 0. Notice this is the beginning of the linear region. (c) Estimate I D at V GS =0.3V and V DS =1.0V. What is the operating region under this bias? Notice that a rough estimate using the subthreshold slope is sufficient here. (4 pts) V GS < V th , and V DS > 3kT/q, and therefore this is the subthreshold saturation region. We will use the subthreshold slope of 60mV/0.8 = 75mV to estimate the current. Given I th =10 μ A at V th =0.7V, with V GS at 0.3V, the current will be: 10 μ A × 10 (0.3 – 0.7)/0.075 = 46.4pA. For perfectionist, you can see the subthreshold line should have a prefactor of 2I th instead of I th . However, in the subthreshold current calculation, we often only need to be correct on the order of magnitude. (d) To obtain I D =10pA with V DS =0.13V, what will be the required V GS ? (4 pts) V DS =0.13V > 3kT/q, so we can assume it is in saturation (independent of V DS ). V GS = V th – 75mV × log 10 (10 μ A/10pA) = 0.25V. 2. (CMOS inverter voltage transfer curve) For a CMOS inverter with a PMOS in the pullup network and a NMOS in the pulldown network, the output is an open circuit. Assume k p ’W p /L p = k n ’W n / L n =1mA/V 2 , V thn = V thp  =1V and V An =V Ap = 10V. V DD = 5V. (a) Plot the load line curves as the output characteristics ( V OUT vs. I D for NMOS and PMOS respectively with V IN as a parameter). Mark the intersections of NMOS and PMOS IV curves for the steadystate solution for V IN = 0, 1, 2, 3, 4, 5V. At those intersections, mark the operation regions (subthreshold, linear or saturation) for NMOS and PMOS. (6 pts) 1 (b) From (a), derive the plot of the voltage transfer curve VTC ( V IN vs. V OUT ). (3 pts) V IN V OUT NMOS PMOS V DD V O for PMOS I V DD V O for NMOS V I =5V V I =4V V I =3V V I =2V V I =1V V I =0V V I =0V V I =1V V I =2V V I =3V V I =4V V I =5V k p ’ W p /L p = k n ’ W n /L n here V IN =0V: NMOS sub V th , PMOS linear V IN =1V: NMOS sat., PMOS linear V IN =2V: NMOS sat., PMOS linear V IN =5V: NMOS linear, PMOS sub V th , V IN =4V: NMOS linear, PMOS sat....
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This note was uploaded on 03/11/2009 for the course ECE 3150 taught by Professor Spencer during the Spring '07 term at Cornell.
 Spring '07
 SPENCER
 Gate, Microelectronics, Volt

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