CPE129_hw9_soln

CPE129_hw9_soln - CPE 129 Homework 9 Solution W. Pilkington...

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CPE 129 Homework 9 Solution W. Pilkington 1) The circuit below shows a use of Tri-State Buffers in a configuration called a “Bus Transceiver”. With this arrangement, a device can use the same signal connections to a shared Data Bus to both send and receive information (Input and Output). The “trick” to this arrangement is controlling the “Output Enable” signals for the tri-state buffers properly, so that the device is never trying to input and output at the same time, and is only doing either when it is its turn to use the bus. In a microcomputer system, this is usually handled by the microprocessor supplying a signal that indicates whether the currently-selected device should “Read” or “Write” (the Rd/Wr signal). The selection of which device should Read or Write with the Data Bus is usually determined by decoding the values on another bus, the “Address Bus” (like A 15 & A 14 below). Design the logic circuits needed to generate the “ OutEnable_L ” (active low) and “ I nEnable_L ” (active low) signals controlling the 2 sets of tri-state buffers, so that the “ Input/Output Device ” works as shown in the following Table. Determine the Boolean logic expression for each of 2 circuits. One circuit has OutEnable_L as its output; the other has I nEnable_L as its output. Both circuits may use any of the following 3 signals for inputs: A 15 , A 14 , Rd/Wr’ D3 D2 D1 D0 OutEnable_L InOut_0 InOut_1
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CPE129_hw9_soln - CPE 129 Homework 9 Solution W. Pilkington...

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