CPE129_hw11V_soln - ENTITY Some_Circuit IS PORT A0 B0 IN STD_LOGIC S0 C0 OUT STD_LOGIC END Some_Circuit What’s Inside the “Black Box”

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CPE 129 Homework 11 “V” (as in VHDL) Solution W. Pilkington 1) Write a complete VHDL Code module for the circuit shown below. Compose both an ENTITY and an ARCHITECTURE description for the circuit. “Some_Circuit” - - Stuff we need to use STD_LOGIC LIBRARY ieee USE ieee.std_logic_1164.all - - The “Black Box”:
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Unformatted text preview: ENTITY Some_Circuit IS PORT ( A0, B0 : IN STD_LOGIC ; S0, C0 : OUT STD_LOGIC ) ; END Some_Circuit ; - - What’s Inside the “Black Box”: ARCHITECTURE Data_Flow OF Some_Circuit IS BEGIN S0 <= A0 XOR B0 ; C0 <= A0 AND B0 ; END Data_Flow ; “……That’s IT??!!. ...It COULDN’T be THAT easy??!!. ...??” C0...
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This note was uploaded on 03/15/2009 for the course CPE 129 taught by Professor Mealy during the Spring '07 term at Cal Poly.

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