CPE129_hw13B_soln

CPE129_hw13B_soln - CPE 129 Homework 13B Solution W....

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CPE 129 Homework 13B Solution W. Pilkington 1. Design a "Parity Checker" for a parallel data receiver using VHDL and a Behavioral architecture . (Reference: Textbook Section 4.4.2) The Parity Checker would be used to verify that data was received properly when it was transmitted from one location to another. This device takes in a 5-bit input, made up of 4 received data bits “ Data(3-0) ” and a received " Parity Bit ". It then compares the parity of the combined 5-bit number with an "expected parity" for the data transmission. This expected parity is determined by another input signal ( ExpectParityOdd / ~ExpectParityEven ). The device generates an output signal that indicates the actual parity of the received 5-bits ( ReceivedParityOdd / ~ReceivedParityEven ), and a signal that indicates if the actual parity of the input matched the expected parity ( Parity OK / ~Parity Error ). Use the diagram below to define the operation of your device: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ParityChecker is Port ( Data : in STD_LOGIC_VECTOR (3 downto 0); ParityBit : in STD_LOGIC; ExpectParityOdd : in STD_LOGIC; ReceivedParityOK : out STD_LOGIC; ReceivedParityOdd : out STD_LOGIC); end ParityChecker; Data(0) Data(1) Data(2) Data(3) ParityBit ExpectParityOdd = 1 : Expect Odd Parity = 0 : Expect Even Parity ReceivedParityOK ReceivedParityOdd = 1 : Received Parity Matches Expected = 0 : Parity Error (Not Matched) = 1 : Received Odd Parity = 0 : Received Even Parity Parity Checker
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CPE 129 Homework 13B Solution W. Pilkington -- ONE POSSIBLE SOLUTION (OF MANY) architecture Behavioral of ParityChecker is begin
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This note was uploaded on 03/15/2009 for the course CPE 129 taught by Professor Mealy during the Spring '07 term at Cal Poly.

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CPE129_hw13B_soln - CPE 129 Homework 13B Solution W....

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