CPE129_hw16_soln

CPE129_hw16_soln - CPE 129 Homework 16 Solution W....

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
CPE 129 Homework 16 Solution W. Pilkington 1. Implement the 1-bit ALU described previously using a structural VHDL design with COMPONENTS for the Half-Adder, Full-Adder, and 4:1 MUXes. [Note: VHDL code for all of these components have already been derived either in CPE 129 Lecture or in CPE 169 Lab (Experiment 7)]. You may use a Concurrent Data-Flow description for the remaining logic functions inside the 1-bit ALU. Use the block diagram below as the basis for your structural design. 1 1 1 Sel(0) Sel(1) Half Adder Full Adder 1 1 CI CI D0 D1 D2 D3 D0 D1 D2 D3 Sel(0) Sel(1) ha_s ha_co fa_s fa_co or_x_out and_x_out M_S0(0) M_S0(1) M_S0(0) M_S0(1) ALU1
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
CPE 129 Homework 16 Solution W. Pilkington VHDL Design of Half-Adder and Full-Adder: Half Adder Full Adder (Writing the VHDL description for these is YOUR job for CPE 169 Experiment #7) ENTITY HA IS -- Half Adder PORT ( A, B : IN STD_LOGIC ; S, CO : OUT STD_LOGIC ) ; END ENTITY HA ; ENTITY FA IS -- Full Adder PORT ( A, B, CI : IN STD_LOGIC ; S, CO : OUT STD_LOGIC ) ; END ENTITY FA ; VHDL Design of 4:1 MUX : (Derived in Lecture) ENTITY MUX_4_to_1 IS PORT ( D0, D1, D2, D3, En
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 6

CPE129_hw16_soln - CPE 129 Homework 16 Solution W....

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online