CPE129_hw18_soln

CPE129_hw18_soln - CPE 129 Homework 18 Solution W....

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CPE 129 Homework 18 Solution W. Pilkington 1. Complete the timing diagram below for the output (Q) of a JK Flip-Flop. Assume that the flip-flop is "negative edge triggered " for the clock input. Assume that the J and K inputs always meet the setup and hold times for the flip-flop. Show the idealized output (no propagation delays). Hold Toggle Reset Toggle Set Toggle Hold Toggle Set
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CPE 129 Homework 18 Solution W. Pilkington 2. Write a VHDL code module (entity and architecture) to implement a JK Flip- Flop. Assume that the flip-flop is "negative edge triggered" for the clock input. The flip-flop also has "active high" asynchronous "Preset" and "Clear" inputs. library IEEE; use IEEE.STD_LOGIC_1164.ALL entity jk_flipflop is port ( J, K , CLK, PRESET, CLR : in std_logic ; Q : out std_logic ); end jk_flipflop; architecture jk_ff_behavior of jk_flipflop is signal tempQ : std_logic := '0' ; -- Intermediate signal to get around problem using -- output Q in an assignment. Initialize to 0. begin
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This note was uploaded on 03/15/2009 for the course CPE 129 taught by Professor Mealy during the Spring '07 term at Cal Poly.

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CPE129_hw18_soln - CPE 129 Homework 18 Solution W....

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