CPE129_hw21b_soln

CPE129_hw21b_soln - CPE 129 Homework 21B Solution W....

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CPE 129 Homework 21B Solution W. Pilkington Finite State Machine Design Synchronous Cumulative Adder : 1) Based on the given State Transition Diagram, write the VHDL code to implement the Synchronous Cumulative Adder. a. Use a “Dependent PS/NS” style Behavioral Architecture, with 2 processes (Synchronous and Combinational processes). b. Use enumerated state encoding in VHDL to implement an Output-Coded State Assignment (state variables = Cumulative_Sum output) to eliminate some of the output logic. c. Implement the Carry_Out signal as a separate Mealy-type output, as shown. d. Include an active-low asynchronous reset signal Reset_L that will force the Adder to reset the Cumulative_Sum to “00”, and begin adding from there. ---------------------------------------------------------------------------------- -- Company: Californeah Polyunsaturated State Univarsity -- Engineer: Professor F.S. MacHine -- -- Module Name: hw21BFSM - Behavioral -- Project Name: Synch_Cumul_Adder_FSM -- Target Devices: Digilent Nexys – Spartan 3 FPGA -- Tool versions: ISE 9.1i -- Description: -- Finite State Machine for Synchronous C -- Cumulative Adder (Assignment #21B) ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Synch_Cumul_Adder_FSM is Port ( X : in STD_LOGIC_VECTOR (1 downto 0); CLK, Reset_L : in STD_LOGIC; Cumulative_Sum : out STD_LOGIC_VECTOR (1 downto 0); Carry_Out : out STD_LOGIC);
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This note was uploaded on 03/15/2009 for the course CPE 129 taught by Professor Mealy during the Spring '07 term at Cal Poly.

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CPE129_hw21b_soln - CPE 129 Homework 21B Solution W....

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