cpe129_s07_ex2

cpe129_s07_ex2 - Name: CPE 129 Spring 2007 Exam 2 Open book...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
Name: CPE 129 Spring 2007 Exam 2 Open book and notes. Show your work and state your assumptions you make for full credit. Point value of problems is listed after problem number (100 pts). Please read the problems carefully . Unless otherwise noted, consider all inputs to be positive logic. 1. (15) Use the schematic diagram to complete the F2 and F1 outputs of the provided timing diagram. Consider the decoder to be a standard 2:4 decoder as modeled by the VHDL code listed below. entity DECODER is Port ( S : in std_logic_vector (1 downto 0); F : out std_logic_vector (3 downto 0)); end DECODER; architecture my_dec of DECODER is begin with SEL select F <= "1000" when "11", "0100" when "10", "0010" when "01", "0001" when "00", "0000" when others ; end my_dec; 2. (15) Draw a circuit that implements the following function: [ ] (H) D) C B )( D A ( F(H) + + + = . Consider the inputs to be: A(H), B(L), C(L), D(H); use only NOR gates and inverters in your solution.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
CPE 129 Spring 2007 Exam 2 page 2 of 4
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 03/15/2009 for the course CPE 129 taught by Professor Mealy during the Spring '07 term at Cal Poly.

Page1 / 4

cpe129_s07_ex2 - Name: CPE 129 Spring 2007 Exam 2 Open book...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online