Unformatted text preview: Score: Name: ECE 3055 A Quiz 1 — Spring 2004 ‘ The following RISC assembly language program is executed on a MIPS processor. Fill in the
register values that will be present, after execution of this program. A summary of MIPS
instructions is included at the bottom of the page — for anyone unfamiliar with the MIPS
instruction set. Prior to execution of the program, memory location 0x0400 contains 0x30552030.
Note: 0x indicates hexadecimal and all answers must be in hexadecimal. A MIPS memory word
or register contains 32-bits. LW $3, 0x0400 SLL $4, $3, 8 0R $2, $3, $4 AND $3, $4, $3 LUI $5, 0x2030 ORI $5, $5, 63 SUB $6, $4, $3 BNE $3, $6., LABEL1 ADDI $6, $0, —4
LABEL1: SW $6, 0x0400 After execution of the MIPS code sequence above, R2 = 0x 3 6 3 O (in hexadecimal) R3=0xi 0 CO 2 0;; O (in hexadecimal)
R4=0x55103 000 (in hexadecimal) R5 =0xlo i O 00 31’:- (in hexadecimal)
Memory Location 0x0400 contains: 0x ff 5 Z O l 0 0 t i (in hexadecimal) The MIPS processor contains thirty-two 32-bit registers, $0 through $31. $0 always contains a zero. By default, all
arithmetic operations use two's complement arithmetic. MIPS Instruction Meanin ADD Rd, Rs, Rt — Rd = Rs + Rt (R — register (53) ) AND Rd, Rs, Rt — Rd = Rs bitwise logical AND Rt (R — register (S) )
OR] Rd, Rs, [named - Rd = Rs bitwise logical OR Immediate value LUl Rd, Immed - Rd = Immediate value high l6-bits. 0's low 16~bits
BEQ Rs, Rt, address - Branch to address, only if Rs equal to Rt LW Rd, address - LOAD - Rd gets contents of memory at address
SLL Rd, Rs, count — Shift left logical (use Off”) by count bits SUB Rd, Rs, Rt - Rd 3 Rs - Rt SW Rd, address - STORE - memory at address gets contents of Rd XOR Rd, Rs, Rt - Rd = Rs bitwise logical XOR Rt ...
View Full Document
- Fall '08