3055q1ds - Score Name ECE 3055 A Quiz 1 — Fall 2004.The...

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Unformatted text preview: Score: Name: ECE 3055 A Quiz 1 — Fall 2004 .The following RISC assembly language program is executed on a MIPS processor. Fill in the register values that will be present, after execution of this program. A summary of MIPS instructions is included at the bottom of the page - for anyone unfamiliar with the MIPS instruction set. Prior to execution of the program, memory location 0x0300 contains 0x20303055. Note: 0x indicates hexadecimal and all answers must be in hexadecimal. A MIPS memory word or register contains 32-bits. LW $3, 0x0300 SRL $4, $3, 4 AND $3, $4, $3 XOR $2, $3, $4 LUI $5, 55 ORI $5, $5, 0x50 ADD $6, $3, $4 BEQ $3, $6, LABEL1 ADDI $6, $6, -10 LABEL1: SW $6, 0x0300 After execution of the MIPS code sequence above, R2=0x 02$ 5 3 03g 12 (inhemdecimal) R3 = OW( in hexadecimal) R4 = 0x020 3 O 3 05 ( in hexadecimal) R5 = 0x00 3 V O O 5 O( in hexadecimal) Memory Location 0x0300 contains: 0x 0 lg 13 O 3 <3 O (in hexadecimal) The MIPS processor contains thirty-two 32-bit registers, $0 through $31. $0 always contains a zero. By default, all arithmetic operations use two’s complement arithmetic. MIPS Instruction Meanin ADD Rd, Rs, Rt - Rd = Rs + Rt (R — register (.3) ) AND Rd, Rs, Rt - Rd = Rs bitwise logical AND Rt (R — register ($)) ORI Rd, Rs, Immed - Rd == Rs bitwise logical 0R Immediate value LUI Rd, Immed - Rd = Immediate value high lfi-bits, 0‘s low 16-bits BEQ Rs, Rt, address - Branch to address, only if Rs equal to Rt LW Rd, address - LOAD - Rd gets contents of memory at address SRL Rd, Rs, count - Shift right logical (use 0 fill) by count bits SUB Rd, Rs, Rt - Rd = Rs - Rt SW Rd, address - STORE - memory at address gets contents of Rd XOR Rd, Rs, Rt - Rd = R5 bitwise logical XOR Rt ...
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