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3055q1f - Score Name ECE 3055 A Quiz I — Spring 2005 The...

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Unformatted text preview: Score: Name: ECE 3055 A Quiz I — Spring 2005 The following, RISC assembly language program is executed on a MIPS processor. Fill in the register values that will be present. after execution of this program. A summary of MIPS instructions is included at the bottom of the page 7 for anyone unfamiliar with the MIPS instruction set. Prior to execution of the program. memory location OxOIOOO contains 0x30552031. Note: Ox indicates hexadecimal and all answers must be in hexadecimal, default is decimal in the MIPS assembly language source file. A MIPS memory word or register" contains 32-bits. Use XXXXXXXX For an undefined value. LW 83, 0x01000 SLL s4. 33, 4 AND s3. s4, 33 ADD sz. 33, S4 LUI $5. 0x3055 OR] 35. $5. 37 SUB ‘56, S4, S3 ENE 53, so, LABEL] ADDI $6. $0. -2 LABEL1: SW 56, 0.x01000 After execution ofthe MIPS code sequence above, fl ,... "I 1 ’3 R2 : OXLI S A 1 Q 3 “— U ( in hexadecimal) 2. is an s- I-’\ R3 : 0x 0 O S O 00 I O ( in I'mrader'r'mrd) P ' R4 : 0xG 2.0 I O ( in firit’adecimm') R5 : 0x 3 O S S O O 1 S- ( in launder-iota!) Memory Location OXOIOOO contains: 0x 0 S O 163 OO ( in hexadecimal) The MIPS processor contains thirty-two 32-bit registers, 30 through S31. 50 always contains a zero. By default. all arithmetic operations use two's complement arithmetic. Assume no branch delay slot is present. rIvHPS Instruction r‘lrlr'mtin" ADD Rd. Rs. Rt - Rd = R5 + Rt (R v register(S}) AND Rd. Rs. Rt — Rd = Rs bitivise logical AND Rt (R «m register (SI) 0R1 Rd. Rs. lrmned - Rd — Rs bitwise logical OR immediate value LU] Rd. [muted — Rd 7 [6-bit Immediate value high lo—liits. [J’s low ID-bits BNE Rs. Rt. address- - Branch to address. only iI'Rs not equal to Rt LW Rd. address - LOAD 7 Rd gels contents ofmcnlory at address SRL Rd. Rs. mum - Shil't right logical (use Ufit'i) by mam! bits SUB Rd. Rs. Rt - Rd — Rs - Rt SW Rd. address — STORE - memory at addrms gets contents of Rd XOR Rd. Rs. Rt - Rd : Rs bitwise logical XOR Rt ...
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