3055q4a - 5 F30 paints Write a complctc VHDL synfilesis...

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Unformatted text preview: 5. F30 paints} Write a complctc VHDL synfilesis modeI fur the digital hardware 513mm in tin: block diagram. Use: a pusitive Edge Clo-ck with a Ember-nus reset. Put all ‘v’I-[DL code inside a single Pro-GEES black. The signal, Bin my or may U131 13: IEquiIEd in 190111 EUdE. Can’t-‘9' ’31. I Dania-1'1 . ELUEELEEEEE lulufhf "’2. 13:3 add 3., fl] aubuact 9"“ W 1 :31 DR ' flELV M EMNfibT b '1; 1T1 “)3 2 Liana ‘L-iti) ULrI L ' Prucasfi 3 HHJCEEi Pit-U of: Resa‘i' —€ Ragfiahr RNIHiE'IQ—r‘ 3 _ 1 . REEEI‘ ’3 £31er 13:1?!qu ”'2 SUE-h Gu-‘r ..‘m+ Pficf'lim flagagfi "5 LIBRARY IEEE; USE IEEE.STD_LDGICF1164.ALL: USE IEEE.STD_LDGIC_HRITH.ALL: USE IEEE.ETD_LOGIC“SIGNED.ALL; ENTITY testlc IS FORTE Datain,(‘.‘nun1: = In ETU_LUEIU_UEUTUE{ 31 UUUUTU U 1,- ELU_Up 3 IN ETU_LUEIU_EEUTUE{ 1 UUUETU {J 1.- Cnntr01,clk,raset : IN STILLOGIC; UUT : UUT ETU_LUUIU_UEUTEE{ 31 DONNTD E II}; END testis; ARCHITECTURE behavior 0F nestle IE EIEUEL Ein, UUT_1nt : ETU_LUEIU_EEUTUEI: 31 UUUUTU U 1.- BEGIN Bin <= UUT_int WHEN Central-‘0' ELSE Count; GUT .-=:= UUT_in1-.,- PRGCESS BEGIN WAIT UNTIL Clk'EVENT END C1k='1’; IF raset=‘1' THEN Dutpmint cs ”UDDDDNDUDDUUDDDDUUUGGUEQDDGUGDDH"3 ELSE ' CASE HLU_Up IS WHEN ”DU" :3 Dut_int <= Datain + Bin; WHEN ”Bl" =3 Dut_int <= Datain — Bin: WHEN "10" =3 Out_int <- Datain DR Bin; WHEN "11" =3 Dut_int <= DatainIED Dawntn D] E “0“: WHEN OTHERS 2: Dut_int <n "DDODDUDUDDDDDDDGDEDUOEDUODDEDDflU"I END CASE; END IF; END PROCESS; END behavior; Caun# ...
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