Unformatted text preview: Score: Name: ECE 3055 Quiz IV Wednesday, September 22, 2004 The following sequence of MIPS instructions is clocked into the pipeline shown on page 404 of your textbook.
Examine this ﬁgure eareﬁilly to see exactly where each signal is located (i.e. before or after pipeline registers). At the
end of Clock cycle 5 when all instructions are in the pipeline, Indicate the resulting values in hexadecimal in the
spaces provided below. Assume all data memory locations contain the word address of the location, and that the
address in any LW/SW instructions below is already shown as a word address (not bytel). Assmne that each register
contains a value equal to the register number prior to execution of this code. List the actual value produced by the
hardware design described in the text — even if the value is not used or saved. and $2, $5, $6 wb _
sw $4,0x200 d” ”l lhlSCOmP ‘G_L;A} 2331 33’??? ll OOIOlOO °°ll0l °l°“‘ FF?
or $2: $5: $6 hit-l" 2— O A '7 Instruction = 0X 7- Q) A W F F F F (2 P‘s) Read Data 1 = OXMLH pt) 090000?) Read Data 2 = 0x (I pt) ALUResult=0x FFF FFFFC’ (1P0 ’Ll‘ (Data Memory) Address = 0x 2‘ O 6 (1 pt) Write Data (input at register ﬁle after mux} = 0x 0 O 0 O O O O kl. (1 pt)
Write Register (Address) = 01: C l (1 pt) ALU control (3-bits in binary) = l \ 0 (1p!) [0 ALU op (2-bits in binary) = (1/2 pt) MemWrite = l (1/2 pt) ...
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