3055q5a-1 - Score Name ECE 3055 Quiz IV Wednesday September...

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Unformatted text preview: Score: Name: ECE 3055 Quiz IV, Wednesday, September 25 Part I: (9 pts.) In the space below, draw a block diagram of the hardware synthesized by the VHDL code found on the additional page provided with the quiz. In the block diagram, include the following: 1. Show all input signals on the left and outputs on the right. 2. Draw each hardware unit in a style similar to the textbook’s block diagrams. 3. Include and clearly indicate any registers, clock signals, and resets. 4. Label all signals with their VHDL signal name (both internal and external). 5. Use a “/” with a number to indicate the Width of any busses (more than 1-bit). 6. Number each of the mux’s input signals with it’s corresponding decimal number (i.e. the value on the mux’s control input signal that selects each input). In uts Hardware Out uts Part II: (Ipt.) Why is internal signal K needed in VHDL? ( xplain) ! ‘ ‘ p ‘ \{OU qu wort {‘chch o c ‘3 gal/“'14 l \B) l“ V HDL SO QM x-.\~\¢r‘v’\al S‘Ugéiml l} l,\‘~.—;mm\ 13'“: ivager‘v fa;- ,J LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY test IS PORT( SIGNAL A, B : OUT STD_LOGIC_VECTOR( 15 DOWNTO 0 ); SIGNAL c, D, E : IN STD_LOGIC_VECTOR( 15 DOWNTO o ); G . SIGNAL F, . IN STD_LOGIC; SIGNAL J : IN STD_LOGIC_VECTOR(1 DOWNTO 0)); END test; ARCHITECTURE behavior OF test IS SIGNAL H, I, K : STD_LOGIC_VECTOR( 15 DOWNTO 0 ); BEGIN A <= H; B <= K; I <= C WHEN J(0) = '0' ELSE D WHEN J(1) = '1' ELSE E; H <= I + K; PROCESS BEGIN WAIT UNTIL ( F'EVENT ) AND ( F = '1' ); IF G = '1' THEN K <= "0000000000000000" ; ELSE K <= H; END IF; END PROCESS; END behavior; ...
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