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Unformatted text preview: CPE 229 Course Notes: Lecture 2 Copyright: 2005 Bryan Mealy VHDL Models As you may remember, the VHDL architecture describes how some VHDL entity will function. The entity therefore does nothing more than describe the interface to the circuit. In other words, the entity describes the signals entering and leaving the circuit. The architecture is comprised of two parts: 1) the declaration section, which is followed by 2) a collection of concurrent statements. There are four main types of concurrent statements: concurrent signal assignment, conditional signal assignment, selected signal assignment, and process statements. There are three different approaches to writing VHDL architectures. These approaches are known as dataflow style , structural style , and behavioral style architectures. The standard approach to learning VHDL is to introduce each of these architectural styles individually and design a few circuits using that style. Although this approach is good from the standpoint of keeping things simple while immersed in the learning process, its also somewhat misleading because more complicated VHDL circuits generally use a mix of these three models. Keep this fact in mind in the following discussion of these models. We will, however, put most of our focus on dataflow and behavioral architectures. Structural modeling is essentially a method to combine a set of VHDL models. For this reason, it is less of a design method and more of an approach for interfacing previously designed modules. The hardest part about using structural models is that youll need to learn some more syntax. This syntax is arguably more straight-forward than the syntax associated with the various concurrent statements weve dealt with up to now. Dataflow Models: A dataflow model specifies a circuit as a concurrent representation of the flow of data through the circuit. In the dataflow approach, circuits are described by showing the input and output relationships between the various built-in components of the VHDL language. The built-in components of VHDL include operators such as AND, OR, XOR, etc. The three forms of concurrent statements weve talked about up until now (concurrent signal assignment, conditional signal assignment, and selective signal assignment) are all statements that are found in dataflow style architectures. If you were to re-examine some of the examples weve done so far, you can in fact see how the data flows through the circuit. These signal assignment statements effectively describe how the data flows from the signals on the right side of the assignment operator (<=) to the signal on the left side of the operator. The dataflow style of architecture has its strong points and weak points. It is good that you can see the flow of data in the circuit by examining the VHDL code. The dataflow models also allow you to make an intelligent guess as to how the actual logic will appear should you decide to synthesize the circuit. In other words, the dataflow style most likely has a significant influence on the synthesized hardware. The dataflow words, the dataflow style most likely has a significant influence on the synthesized hardware....
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This note was uploaded on 03/27/2009 for the course CPE 229 taught by Professor Smith during the Spring '09 term at Cal Poly.
- Spring '09