cpe229_lec05 - CPE 229 Course Notes Lecture 5 Copyright...

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CPE 229 Course Notes: Lecture 5 Copyright: 2005 Bryan Mealy A Quick Overview of Things Up until this point in CPE 229, our discussion of FSMs has been primarily centered on both design and analysis. We knew that the storage elements (the flip-flops) were edge-triggered which allowed transitions between states to only occur on the associated clock edges. We also had several flip-flops to choose from (D, T, and JK) when implementing our FSMs 1 . The FSMs were defined with either a PS/NS table or a state diagram (both presented the same information but in a different format). The FSMs had external inputs and external outputs which were generally named with X and Z variables, respectively. The external outputs could either be Moore-type or Mealy-type; both outputs were a function of the present state of the FSM but Mealy- type outputs were also a function of external inputs. And finally, we knew that ultimately, the FSM would be used to control some other circuit. The external inputs (X) would provide information to the FSM which would subsequently be used to synthesize control signals on the FSM’s output variables (Z). And despite what several other faculty members think, there is more to FSMs than designing counters of various types. In this day and age, when you think about control, maybe the most straight-forward way to control another circuit is under the software control of a microcontroller (MCU). In this context, it would generally not make sense to have a FSM do the control function since it would require hardware that was not included on the MCU package. But, also in this day and age, MCUs are implemented on FPGAs (known as softcore processor). In this case, there could be unused logic on the FPGA that could be used to implement a FSM as a form of control of some circuit. This would be good because some of the control requirements could be transitioned to hardware (external FSM) which would most likely have the effect of simplifying the MCU’s software. The study of FSMs can be broken into three parts. You know the first part: the design and analysis of FSMs. The second part is to develop a basic understanding of state diagrams which is what this set of notes deals with. The final part is to design your own FSMs from a given specification. That will be in later sets of notes. Up until now, we really have not mentioned too much about FSM timing considerations. Possibly our only mention of the timing associated with the FSMs was that the state transitions only occurred on a clock edge. In reality, you’re missing a big part of the story: the underlying timing diagram. The importance of timing diagrams was unfortunately passed over by the required CPE 129 textbook 2 . This set of notes is primarily concerned with timing diagrams and their relation to FSMs. And since FSMs are defined rather nicely with state diagrams, this will be the best place to start this discussion. From any state diagram, an associated timing diagram can be generated. Timing Diagrams and State Diagrams
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This note was uploaded on 03/27/2009 for the course CPE 229 taught by Professor Smith during the Spring '09 term at Cal Poly.

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cpe229_lec05 - CPE 229 Course Notes Lecture 5 Copyright...

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